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[Qemu-devel] [PATCH v5 03/23] target-arm/translate.c: Use get_mem_index(
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 03/23] target-arm/translate.c: Use get_mem_index() for SRS memory accesses |
Date: |
Sun, 25 May 2014 11:08:32 +1000 |
From: Peter Maydell <address@hidden>
The SRS instruction was using a hardcoded 0 for the memory
accesses. This happens to be OK since the SRS instruction is
UNPREDICTABLE in User and System modes, but is awkward if we
want to rearrange the MMU index uses. Switch to using
get_mem_index() like all the other accesses.
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e708f4a..e40b0a7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7338,11 +7338,11 @@ static void gen_srs(DisasContext *s,
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = load_reg(s, 14);
- gen_aa32_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, get_mem_index(s));
tcg_temp_free_i32(tmp);
tmp = load_cpu_field(spsr);
tcg_gen_addi_i32(addr, addr, 4);
- gen_aa32_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, get_mem_index(s));
tcg_temp_free_i32(tmp);
if (writeback) {
switch (amode) {
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/23] target-arm: Preparations for A64 EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 01/23] target-arm: Move get_mem_index to translate.h, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 02/23] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 03/23] target-arm/translate.c: Use get_mem_index() for SRS memory accesses,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 04/23] target-arm: A32: Use get_mem_index for load/stores, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 05/23] target-arm: Use a 1:1 mapping between EL and MMU index, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 07/23] target-arm: Make esr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[], Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 09/23] target-arm: A64: Add SP entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 10/23] target-arm: A64: Add ELR entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 11/23] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 13/23] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/24