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[Qemu-devel] [PATCH 12/20] target-i386: set correct error code for reser
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 12/20] target-i386: set correct error code for reserved bit access |
Date: |
Tue, 27 May 2014 15:23:10 +0200 |
The correct error code is 9 (present, reserved), not 8.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/helper.c | 26 +++++++++-----------------
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 5a50364..a8e4088 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -530,7 +530,8 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
CPUX86State *env = &cpu->env;
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
- int error_code, is_dirty, prot, page_size, is_write, is_user;
+ int error_code = 0;
+ int is_dirty, prot, page_size, is_write, is_user;
hwaddr paddr;
uint32_t page_offset;
target_ulong vaddr, virt_addr;
@@ -577,12 +578,10 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pml4e = ldq_phys(cs->as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
- error_code = PG_ERROR_RSVD_MASK;
- goto do_fault;
+ goto do_fault_rsvd;
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
@@ -593,12 +592,10 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
- error_code = PG_ERROR_RSVD_MASK;
- goto do_fault;
+ goto do_fault_rsvd;
}
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
@@ -620,7 +617,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
@@ -630,12 +626,10 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pde = ldq_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
- error_code = PG_ERROR_RSVD_MASK;
- goto do_fault;
+ goto do_fault_rsvd;
}
ptep &= pde ^ PG_NX_MASK;
if (pde & PG_PSE_MASK) {
@@ -654,12 +648,10 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pte = ldq_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
- error_code = PG_ERROR_RSVD_MASK;
- goto do_fault;
+ goto do_fault_rsvd;
}
/* combine pde and pte nx, user and rw protections */
ptep &= pte ^ PG_NX_MASK;
@@ -672,7 +664,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pde = ldl_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
ptep = pde | PG_NX_MASK;
@@ -695,7 +686,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->a20_mask;
pte = ldl_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
- error_code = 0;
goto do_fault;
}
/* combine pde and pte user and rw protections */
@@ -776,8 +766,10 @@ do_check_protect:
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
+ do_fault_rsvd:
+ error_code |= PG_ERROR_RSVD_MASK;
do_fault_protect:
- error_code = PG_ERROR_P_MASK;
+ error_code |= PG_ERROR_P_MASK;
do_fault:
error_code |= (is_write << PG_ERROR_W_BIT);
if (is_user)
--
1.8.3.1
- [Qemu-devel] [PATCH 02/20] target-i386: move check_io helpers to seg_helper.c, (continued)
- [Qemu-devel] [PATCH 02/20] target-i386: move check_io helpers to seg_helper.c, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 03/20] target-i386: fix kernel accesses with SMAP and CPL = 3, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 04/20] target-i386: simplify SMAP handling in MMU_KSMAP_IDX, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 01/20] target-i386: rename KSMAP to KNOSMAP, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 05/20] target-i386: fix coding standards in x86_cpu_handle_mmu_fault, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 06/20] target-i386: commonize checks for 2MB and 4KB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 07/20] target-i386: commonize checks for 4MB and 4KB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 08/20] target-i386: commonize checks for PAE and non-PAE, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 10/20] target-i386: introduce do_check_protect label, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 09/20] target-i386: tweak handling of PG_NX_MASK, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 12/20] target-i386: set correct error code for reserved bit access,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 13/20] target-i386: test reserved PS bit on PML4Es, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 11/20] target-i386: introduce support for 1 GB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 14/20] target-i386: raise page fault for reserved physical address bits, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 15/20] target-i386: simplify pte/vaddr calculation, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 16/20] target-i386: unify reserved bits and NX bit check, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 17/20] target-i386: raise page fault for reserved bits in large pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 18/20] target-i386: support long addresses for 4MB pages (PSE-36), Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 19/20] target-i386: fix protection bits in the TLB for SMEP, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 20/20] target-i386: cleanup x86_cpu_get_phys_page_debug, Paolo Bonzini, 2014/05/27