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[Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and E
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON |
Date: |
Tue, 27 May 2014 17:28:22 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 4 +++-
target-arm/helper.c | 4 ++++
target-arm/machine.c | 6 +++---
target-arm/translate.c | 4 ++--
4 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 60414ac..5919dfd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -143,7 +143,7 @@ typedef struct CPUARMState {
uint32_t spsr;
/* Banked registers. */
- uint64_t banked_spsr[6];
+ uint64_t banked_spsr[8];
uint32_t banked_r13[6];
uint32_t banked_r14[6];
@@ -563,7 +563,9 @@ enum arm_cpu_mode {
ARM_CPU_MODE_FIQ = 0x11,
ARM_CPU_MODE_IRQ = 0x12,
ARM_CPU_MODE_SVC = 0x13,
+ ARM_CPU_MODE_MON = 0x16,
ARM_CPU_MODE_ABT = 0x17,
+ ARM_CPU_MODE_HYP = 0x1a,
ARM_CPU_MODE_UND = 0x1b,
ARM_CPU_MODE_SYS = 0x1f
};
diff --git a/target-arm/helper.c b/target-arm/helper.c
index eb5a832..368413c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3108,6 +3108,10 @@ int bank_number(int mode)
return 4;
case ARM_CPU_MODE_FIQ:
return 5;
+ case ARM_CPU_MODE_HYP:
+ return 6;
+ case ARM_CPU_MODE_MON:
+ return 7;
}
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
}
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 233e70d..3bcc7cc 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
- .version_id = 19,
- .minimum_version_id = 19,
+ .version_id = 20,
+ .minimum_version_id = 20,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@@ -233,7 +233,7 @@ const VMStateDescription vmstate_arm_cpu = {
.offset = 0,
},
VMSTATE_UINT32(env.spsr, ARMCPU),
- VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6),
+ VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 08732a0..c2dfbfe 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11052,8 +11052,8 @@ void gen_intermediate_code_pc(CPUARMState *env,
TranslationBlock *tb)
}
static const char *cpu_mode_names[16] = {
- "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
- "???", "???", "???", "und", "???", "???", "???", "sys"
+ "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
+ "???", "???", "hyp", "und", "???", "???", "???", "sys"
};
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
--
1.9.2
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, (continued)
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(), Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON,
Peter Maydell <=
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 09/26] target-arm: Make elr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h, Peter Maydell, 2014/05/27