Re: [Qemu-devel] [PATCH v2 5/8] target-arm: implement SCTLR.EE

[Peter Maydell]

On 29 May 2014 20:46, Paolo Bonzini <address@hidden> wrote:
> Set CPSR.E to SCTLR.EE on exception, and use SCTLR.EE also to
> determine endianness for loads during TLB misses.
>
> Signed-off-by: Paolo Bonzini <address@hidden>
> ---
>  target-arm/helper.c | 38 ++++++++++++++++++++++++++++++++------
>  1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 95af624..0ea8553 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3202,6 +3202,30 @@ void switch_mode(CPUARMState *env, int mode)
>      env->spsr = env->banked_spsr[i];
>  }
>
> +static uint32_t ldl_kernel(CPUState *cs, target_ulong physaddr)
> +{
> +    ARMCPU *cpu = ARM_CPU(cs);
> +    CPUARMState *env = &cpu->env;
> +
> +    if (unlikely(env->cp15.c1_sys & SCTLR_EE)) {
> +        return ldl_be_phys(cs->as, physaddr);
> +    } else {
> +        return ldl_le_phys(cs->as, physaddr);
> +    }
> +}

The ARM ARM calls this kind of access a page table walk
access (AccType_PTW in the AccType enumeration). I'd
prefer to call these ldl_ptw_phys and stl_ptw_phys. ('kernel'
implies "all EL1 accesses are like this", which they aren't.)

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM