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[Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation |
Date: |
Wed, 4 Jun 2014 14:44:08 +0200 |
In addition to the L1 data cache configuration register L1CFG0 there is
also another one for the L1 instruction cache called L1CFG1.
Emulate that one with the same values as the data one.
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 178fc55..f36c90b 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1375,6 +1375,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
#define SPR_Exxx_L1CFG0 (0x203)
+#define SPR_Exxx_L1CFG1 (0x204)
#define SPR_Exxx_NPIDR (0x205)
#define SPR_ATBL (0x20E)
#define SPR_ATBU (0x20F)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 07f723d..fc9d932 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4651,6 +4651,8 @@ static void init_proc_e500 (CPUPPCState *env, int version)
uint64_t ivpr_mask = 0xFFFF0000ULL;
uint32_t l1cfg0 = 0x3800 /* 8 ways */
| 0x0020; /* 32 kb */
+ uint32_t l1cfg1 = 0x3800 /* 8 ways */
+ | 0x0020; /* 32 kb */
#if !defined(CONFIG_USER_ONLY)
int i;
#endif
@@ -4719,6 +4721,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
env->dcache_line_size = 64;
env->icache_line_size = 64;
l1cfg0 |= 0x1000000; /* 64 byte cache block size */
+ l1cfg1 |= 0x1000000; /* 64 byte cache block size */
break;
default:
cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
env->spr[SPR_PVR]);
@@ -4769,7 +4772,10 @@ static void init_proc_e500 (CPUPPCState *env, int
version)
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
l1cfg0);
- /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ l1cfg1);
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_e500_l1csr0,
--
1.8.1.4
- [Qemu-devel] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, (continued)
- [Qemu-devel] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 049/118] target-ppc: Introduce DFP Extract Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their temps, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 063/118] PPC: Fail on leaking temporaries, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 051/118] target-ppc: Introduce DFP Shift Significand, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 060/118] PPC: e500: some pci related cleanup, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 055/118] util: Add InvMixColumns, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation,
Alexander Graf <=
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/23
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/23
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/23