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[Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables |
Date: |
Mon, 9 Jun 2014 15:57:23 +0100 |
From: Ian Campbell <address@hidden>
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.
Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.
This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.
Signed-off-by: Ian Campbell <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Claudio Fontana <address@hidden>
Cc: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 147521e..d32d120 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3955,13 +3955,8 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
page_size = (1 << ((granule_sz * (4 - level)) + 3));
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor and merge with table attrs */
- if (arm_feature(env, ARM_FEATURE_V8)) {
- attrs = extract64(descriptor, 2, 10)
- | (extract64(descriptor, 53, 11) << 10);
- } else {
- attrs = extract64(descriptor, 2, 10)
- | (extract64(descriptor, 52, 12) << 10);
- }
+ attrs = extract64(descriptor, 2, 10)
+ | (extract64(descriptor, 52, 12) << 10);
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
@@ -3987,8 +3982,12 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
goto do_fault;
}
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
- /* XN or PXN */
+ if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
+ (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
+ (!is_user && (attrs & (1 << 11)))) {
+ /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
+ * treat XN/UXN as UXN for v8.
+ */
if (access_type == 2) {
goto do_fault;
}
--
1.9.2
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper, (continued)
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables,
Peter Maydell <=
- [Qemu-devel] [PULL 12/20] target-arm: Clean up handling of ARMv8 optional feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 02/20] target-arm/cpu64.c: Actually register Cortex-A57 impdef registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 04/20] target-arm: implement PD0/PD1 bits for TTBCR, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 01/20] vexpress: Add support for the -bios flag to provide firmware, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 06/20] target-arm: add support for v8 SHA1 and SHA256 instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 03/20] target-arm: Prepare cpreg writefns/readfns for EL3/SecExt, Peter Maydell, 2014/06/09