Re: [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3

[Edgar E. Iglesias]

On Tue, Jun 17, 2014 at 07:12:19AM +0000, Aggeler  Fabian wrote:
> 
> On 17 Jun 2014, at 07:40, Edgar E. Iglesias <address@hidden> wrote:
> 
> > On Wed, Jun 11, 2014 at 01:54:48AM +0200, Fabian Aggeler wrote:
> >> Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
> >> Increase MMU modes since mmu_index is directly infered from arm_
> >> current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
> >> 
> >> Signed-off-by: Fabian Aggeler <address@hidden>
> >> ---
> >> target-arm/cpu.h | 15 +++++++++------
> >> 1 file changed, 9 insertions(+), 6 deletions(-)
> >> 
> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> >> index cb0da6b..14007a9 100644
> >> --- a/target-arm/cpu.h
> >> +++ b/target-arm/cpu.h
> >> @@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int 
> >> cp_info,
> >> 
> >> struct arm_boot_info;
> >> 
> >> -#define NB_MMU_MODES 2
> >> +#define NB_MMU_MODES 4
> > 
> > I guess this was unintentional here?
> 
> Not really. Well, it was first in a separate commit but I squashed it. We 
> need to increase
> the number of MMU_MODES to 4 because arm_current_pl() now returns 3 for 
> monitor
> mode and secure PL1 (Aarch32) and EL3 (Aarch64), which is directly used as 
> mmu_index
> since your last patchset. Is my reasoning wrong?


Aha I see. Nah I think you are correct, I was just surprised that it wasn't
a separate patch.

Thanks,
Edgar


> 
> 
> > 
> > 
> >> 
> >> /* We currently assume float and double are IEEE single and double
> >>    precision respectively.
> >> @@ -710,7 +710,6 @@ static inline int arm_feature(CPUARMState *env, int 
> >> feature)
> >>     return (env->features & (1ULL << feature)) != 0;
> >> }
> >> 
> >> -
> > 
> > This too.
> > 
> > 
> >> /* Return true if exception level below EL3 is in secure state */
> >> static inline bool arm_is_secure_below_el3(CPUARMState *env)
> >> {
> >> @@ -751,11 +750,12 @@ static inline bool arm_is_secure(CPUARMState *env)
> >> /* Return true if the specified exception level is running in AArch64 
> >> state. */
> >> static inline bool arm_el_is_aa64(CPUARMState *env, int el)
> >> {
> >> -    /* We don't currently support EL2 or EL3, and this isn't valid for EL0
> >> +    /* We don't currently support EL2, and this isn't valid for EL0
> >>      * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
> >>      * then the state of EL0 isn't well defined.)
> >>      */
> >> -    assert(el == 1);
> >> +    assert(el == 1 || el == 3);
> >> +
> >>     /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
> >>      * is a QEMU-imposed simplification which we may wish to change later.
> >>      * If we in future support EL2 and/or EL3, then the state of lower
> >> @@ -947,9 +947,12 @@ static inline int arm_current_pl(CPUARMState *env)
> >> 
> >>     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
> >>         return 0;
> >> +    } else if (arm_is_secure(env)) {
> >> +        /* Secure PL1 and monitor mode are mapped to PL3 */
> >> +        return 3;
> >>     }
> >> -    /* We don't currently implement the Virtualization or TrustZone
> >> -     * extensions, so PL2 and PL3 don't exist for us.
> >> +    /* We currently do not implement the Virtualization extensions, so 
> >> PL2 does
> >> +     * not exist for us.
> >>      */
> >>     return 1;
> >> }
> >> -- 
> >> 1.8.3.2
>