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[Qemu-devel] [RFC PATCH] target-ppc: Add compatibility between P7/P7+ an
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From: |
Alexey Kardashevskiy |
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Subject: |
[Qemu-devel] [RFC PATCH] target-ppc: Add compatibility between P7/P7+ and P8E/P8 |
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Date: |
Sat, 28 Jun 2014 01:54:40 +1000 |
At the moment POWER7+ and POWER7 CPUs are different incompatible
families in QOM. The same is valid for POWER8E and POWER8 CPUs.
However, these couples are architecturally equal and there is no
good reason, for example, not to let run -cpu POWER7 on the real
POWER7+ CPU machine.
This introduces one more level in hierarchy of POWERPC CPU classes.
New macro POWERPC_FAMILY_2 takes a family class and the parent family
class and, for example, for POWER7+ the hierarchy looks like:
TYPE_CPU
TYPE_POWERPC_CPU
POWER7-powerpc64-cpu
POWER7+-powerpc64-cpu
This registers new dynamic POWERPC CPU classes for all classes between
the lowest one which matches the real PVR and TYPE_POWERPC_CPU.
So for POWER7, it is still going to be just a single dynamic "POWER7"
class but for POWER7+ inherited from POWER7 there are going to be
2 dynamic classes - "POWER7+" and "POWER7" so management software
can use both to ensure successful migration.
Since POWER7+ inherits from POWER7 and POWER8E from POWER8, this
removes recurring pieces of code. CPUs with shorter names were chosen
as parents.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
This is rather RFC patch and there is no hurry in reviewing this,
and this is not 2.1 material and everyhting, just tried to solve
a QOM puzzle here :)
---
target-ppc/kvm.c | 28 ++++++----------
target-ppc/translate_init.c | 82 +++++++++++----------------------------------
2 files changed, 30 insertions(+), 80 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 2d87108..7033c1e 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -38,6 +38,7 @@
#include "hw/ppc/ppc.h"
#include "sysemu/watchdog.h"
#include "trace.h"
+#include "cpu-models.h"
//#define DEBUG_KVM
@@ -1828,18 +1829,6 @@ bool kvmppc_has_cap_fixup_hcalls(void)
return cap_fixup_hcalls;
}
-static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
-{
- ObjectClass *oc = OBJECT_CLASS(pcc);
-
- while (oc && !object_class_is_abstract(oc)) {
- oc = object_class_get_parent(oc);
- }
- assert(oc);
-
- return POWERPC_CPU_CLASS(oc);
-}
-
static int kvm_ppc_register_host_cpu_type(void)
{
TypeInfo type_info = {
@@ -1850,6 +1839,7 @@ static int kvm_ppc_register_host_cpu_type(void)
uint32_t host_pvr = mfpvr();
PowerPCCPUClass *pvr_pcc;
DeviceClass *dc;
+ ObjectClass *oc;
pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
if (pvr_pcc == NULL) {
@@ -1862,11 +1852,15 @@ static int kvm_ppc_register_host_cpu_type(void)
type_register(&type_info);
/* Register generic family CPU class for a family */
- pvr_pcc = ppc_cpu_get_family_class(pvr_pcc);
- dc = DEVICE_CLASS(pvr_pcc);
- type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
- type_info.name = g_strdup_printf("%s-"TYPE_POWERPC_CPU, dc->desc);
- type_register(&type_info);
+ while (pvr_pcc && (pvr_pcc->pvr_mask != CPU_POWERPC_DEFAULT_MASK)) {
+ dc = DEVICE_CLASS(pvr_pcc);
+ oc = OBJECT_CLASS(pvr_pcc);
+ type_info.parent = object_class_get_name(oc);
+ type_info.name = g_strdup_printf("%s-"TYPE_POWERPC_CPU, dc->desc);
+ type_register(&type_info);
+
+ pvr_pcc = POWERPC_CPU_CLASS(object_class_get_parent(oc));
+ }
return 0;
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a3bb336..665c6f8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3135,14 +3135,14 @@ static bool
ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
/*****************************************************************************/
/* PowerPC implementations definitions */
-#define POWERPC_FAMILY(_name) \
+#define __POWERPC_FAMILY_PARENT(_name, _parent_class) \
static void \
glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
\
static const TypeInfo \
glue(glue(ppc_, _name), _cpu_family_type_info) = { \
.name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
- .parent = TYPE_POWERPC_CPU, \
+ .parent = _parent_class, \
.abstract = true, \
.class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
}; \
@@ -3157,6 +3157,13 @@ static bool
ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
\
static void glue(glue(ppc_, _name), _cpu_family_class_init)
+#define POWERPC_FAMILY(_name) \
+ __POWERPC_FAMILY_PARENT(_name, TYPE_POWERPC_CPU)
+
+#define POWERPC_FAMILY_2(_name, _parent_name) \
+ __POWERPC_FAMILY_PARENT(_name, \
+ stringify(_parent_name) "-family-"
TYPE_POWERPC_CPU)
+
static void init_proc_401 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -8123,65 +8130,16 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
-POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
+POWERPC_FAMILY_2(POWER7P, POWER7)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->fw_name = "PowerPC,POWER7+";
dc->desc = "POWER7+";
- dc->props = powerpc_servercpu_properties;
pcc->pvr = CPU_POWERPC_POWER7P_BASE;
pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
- pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
- pcc->init_proc = init_proc_POWER7;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_FRSQRTES |
- PPC_FLOAT_STFIWX |
- PPC_FLOAT_EXT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI |
- PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
- PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_VR) |
- (1ull << MSR_VSX) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_2_06;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_POWER7;
- pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x8000;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8189,16 +8147,16 @@ static void init_proc_POWER8(CPUPPCState *env)
init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
}
-POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data)
+POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->fw_name = "PowerPC,POWER8";
- dc->desc = "POWER8E";
+ dc->desc = "POWER8";
dc->props = powerpc_servercpu_properties;
- pcc->pvr = CPU_POWERPC_POWER8E_BASE;
- pcc->pvr_mask = CPU_POWERPC_POWER8E_MASK;
+ pcc->pvr = CPU_POWERPC_POWER8_BASE;
+ pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
pcc->init_proc = init_proc_POWER8;
pcc->check_pow = check_pow_nocheck;
@@ -8253,16 +8211,14 @@ POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
-POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
+POWERPC_FAMILY_2(POWER8E, POWER8)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- ppc_POWER8E_cpu_family_class_init(oc, data);
-
- dc->desc = "POWER8";
- pcc->pvr = CPU_POWERPC_POWER8_BASE;
- pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
+ dc->desc = "POWER8E";
+ pcc->pvr = CPU_POWERPC_POWER8E_BASE;
+ pcc->pvr_mask = CPU_POWERPC_POWER8E_MASK;
}
#endif /* defined (TARGET_PPC64) */
--
2.0.0
- [Qemu-devel] [RFC PATCH] target-ppc: Add compatibility between P7/P7+ and P8E/P8,
Alexey Kardashevskiy <=