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[Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate C
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs |
Date: |
Mon, 30 Jun 2014 18:09:33 -0500 |
From: Greg Bellows <address@hidden>
This patch adds code to mark duplicate CP register registrations as NO_MIGRATE
to avoid duplicate migrations.
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3bc55fe..7c1e2eb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2339,7 +2339,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.access = PL3_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
.resetvalue = 0 },
- { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
+ /* SCR will always be registered for v7, but not necessarily for v8, so
+ * this entry is marked to allow migration to be handled by the v7
+ * registration instance.
+ */
+ { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.writefn = scr_write },
@@ -2958,6 +2962,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
* banked registers but later only fieldoffset is used.
*/
r2->fieldoffset = r->bank_fieldoffsets[nsbit];
+ } else if (!nsbit) {
+ /* The register is not banked so we only want to allow migration of
+ * the non-secure instance.
+ */
+ r2->type |= ARM_CP_NO_MIGRATE;
}
if (r->state == ARM_CP_STATE_BOTH) {
--
1.8.3.2
- [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked, (continued)
- [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs,
greg . bellows <=
- [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked, greg . bellows, 2014/06/30