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[Qemu-devel] [PATCH v2 01/10] target-arm/cpu.h: document various program
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v2 01/10] target-arm/cpu.h: document various program state functions |
Date: |
Thu, 10 Jul 2014 16:49:58 +0100 |
We have a number of program state saving functions (pstate, cpsr, xpsr)
which are dependant on the mode the CPU is in. This commit adds a little
documentation to each function and asserts to defend against incorrect
use.
Signed-off-by: Alex Bennée <address@hidden>
---
v2:
- remove xpsr_state asserts
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 369d472..c2312d0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -475,22 +475,34 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr
address, int rw,
#define PSTATE_MODE_EL1t 4
#define PSTATE_MODE_EL0t 0
-/* Return the current PSTATE value. For the moment we don't support 32<->64 bit
- * interprocessing, so we don't attempt to sync with the cpsr state used by
- * the 32 bit decoder.
+/* ARMv8 ARM D1.7 Process state, PSTATE
+ *
+ * 31 28 27 24 23 22 21 20 22 21 20 19 16 15 8 7 5 4 0
+ * +------+------+-------+-----+--------+---+------+------+-----+------+
+ * | NZCV | DAIF | SS IL | EL | nRW SP | Q | GE | IT | JTE | Mode |
+ * +------+------+-------+-----+--------+---+------+------+-----+------+
+ *
+ * The PSTATE is an abstraction of a number of Return the current
+ * PSTATE value. This is only valid for A64 hardware although can be
+ * read when in AArch32 mode.
*/
static inline uint32_t pstate_read(CPUARMState *env)
{
int ZF;
+ g_assert(is_a64(env));
+
ZF = (env->ZF == 0);
return (env->NF & 0x80000000) | (ZF << 30)
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
| env->pstate | env->daif;
}
+/* Update the current PSTATE value. This doesn't include nRW which is */
static inline void pstate_write(CPUARMState *env, uint32_t val)
{
+ g_assert(is_a64(env));
+
env->ZF = (~val) & PSTATE_Z;
env->NF = val;
env->CF = (val >> 29) & 1;
@@ -499,15 +511,22 @@ static inline void pstate_write(CPUARMState *env,
uint32_t val)
env->pstate = val & ~CACHED_PSTATE_BITS;
}
-/* Return the current CPSR value. */
+/* ARMv7-AR ARM B1.3.3 Current Program Status Register, CPSR
+ *
+ * Unlike the above PSTATE implementation these functions will attempt
+ * to switch processor mode when the M[4:0] bits are set.
+ */
uint32_t cpsr_read(CPUARMState *env);
/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
-/* Return the current xPSR value. */
+/* ARMv7-M ARM B1.4.2, special purpose program status register xPSR */
static inline uint32_t xpsr_read(CPUARMState *env)
{
int ZF;
+
+ g_assert(!is_a64(env));
+
ZF = (env->ZF == 0);
return (env->NF & 0x80000000) | (ZF << 30)
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
@@ -519,6 +538,8 @@ static inline uint32_t xpsr_read(CPUARMState *env)
/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
+ g_assert(!is_a64(env));
+
if (mask & CPSR_NZCV) {
env->ZF = (~val) & CPSR_Z;
env->NF = val;
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 2b4ce6a..ec1fef5 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -506,8 +506,8 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->condexec_bits = 0;
}
- pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h);
env->aarch64 = 1;
+ pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h);
env->pc = addr;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
--
2.0.1
- [Qemu-devel] [PATCH v2 00/10] aarch64 migration for TCG and KVM, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 01/10] target-arm/cpu.h: document various program state functions,
Alex Bennée <=
- [Qemu-devel] [PATCH v2 02/10] target-arm/cpu.h: common pstate save/restore, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 03/10] target-arm: Support save/load for 64 bit CPUs, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 04/10] target-arm: replace cpsr/xpsr/pstate_read calls, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 05/10] arm/nwfps: replace cpsr_write with set_condition_codes, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 06/10] linux-user/main.c: __kernel_cmpxchg set env->CF directly, Alex Bennée, 2014/07/10
- [Qemu-devel] [PATCH v2 07/10] target-arm: remove last users of cpsr_write, Alex Bennée, 2014/07/10