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[Qemu-devel] [PATCH v3 28/32] ahci: add test_pci_enable to ahci-test.
From: |
John Snow |
Subject: |
[Qemu-devel] [PATCH v3 28/32] ahci: add test_pci_enable to ahci-test. |
Date: |
Wed, 13 Aug 2014 17:56:11 -0400 |
This adds a test wherein we engage the PCI AHCI
device and ensure that the memory region for the
HBA functionality is now accessible.
Under Q35 environments, additional PCI configuration
is performed to ensure that the HBA functionality
will become usable.
Signed-off-by: John Snow <address@hidden>
---
tests/ahci-test.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
tests/libqos/pci.c | 6 ++++++
2 files changed, 63 insertions(+)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index 29ac0d0..0ca4a20 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -56,6 +56,7 @@
/*** Globals ***/
static QGuestAllocator *guest_malloc;
static QPCIBus *pcibus;
+static uint64_t barsize;
static char tmp_path[] = "/tmp/qtest.XXXXXX";
static bool ahci_pedantic;
static uint32_t ahci_fingerprint;
@@ -66,6 +67,7 @@ static uint32_t ahci_fingerprint;
/*** Function Declarations ***/
static QPCIDevice *get_ahci_device(void);
+static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base);
static void free_ahci_device(QPCIDevice *dev);
static void ahci_test_pci_spec(QPCIDevice *ahci);
static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
@@ -111,6 +113,9 @@ static void free_ahci_device(QPCIDevice *ahci)
qpci_free_pc(pcibus);
pcibus = NULL;
}
+
+ /* Clear our cached barsize information. */
+ barsize = 0;
}
/*** Test Setup & Teardown ***/
@@ -169,6 +174,44 @@ static void ahci_shutdown(QPCIDevice *ahci)
qtest_shutdown();
}
+/*** Logical Device Initialization ***/
+
+/**
+ * Start the PCI device and sanity-check default operation.
+ */
+static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base)
+{
+ uint8_t reg;
+
+ start_ahci_device(ahci, hba_base);
+
+ switch(ahci_fingerprint) {
+ case AHCI_INTEL_ICH9:
+ /* ICH9 has a register at PCI 0x92 that
+ * acts as a master port enabler mask. */
+ reg = qpci_config_readb(ahci, 0x92);
+ reg |= 0x3F;
+ qpci_config_writeb(ahci, 0x92, reg);
+ assert_bit_set(qpci_config_readb(ahci, 0x92), 0x3F);
+ break;
+ }
+
+}
+
+/**
+ * Map BAR5/ABAR, and engage the PCI device.
+ */
+static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base)
+{
+ /* Map AHCI's ABAR (BAR5) */
+ *hba_base = qpci_iomap(ahci, 5, &barsize);
+
+ /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
+ qpci_device_enable(ahci);
+
+ return ahci;
+}
+
/*** Specification Adherence Tests ***/
/**
@@ -428,6 +471,19 @@ static void test_pci_spec(void)
ahci_shutdown(ahci);
}
+/**
+ * Engage the PCI AHCI device and sanity check the response.
+ * Perform additional PCI config space bringup for the HBA.
+ */
+static void test_pci_enable(void)
+{
+ QPCIDevice *ahci;
+ void *hba_base;
+ ahci = ahci_boot();
+ ahci_pci_enable(ahci, &hba_base);
+ ahci_shutdown(ahci);
+}
+
/******************************************************************************/
int main(int argc, char **argv)
@@ -479,6 +535,7 @@ int main(int argc, char **argv)
/* Run the tests */
qtest_add_func("/ahci/sanity", test_sanity);
qtest_add_func("/ahci/pci_spec", test_pci_spec);
+ qtest_add_func("/ahci/pci_enable", test_pci_enable);
ret = g_test_run();
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
index ce0b308..b244689 100644
--- a/tests/libqos/pci.c
+++ b/tests/libqos/pci.c
@@ -73,6 +73,12 @@ void qpci_device_enable(QPCIDevice *dev)
cmd = qpci_config_readw(dev, PCI_COMMAND);
cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
qpci_config_writew(dev, PCI_COMMAND, cmd);
+
+ /* Verify the bits are now set. */
+ cmd = qpci_config_readw(dev, PCI_COMMAND);
+ g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
+ g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
+ g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
}
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
--
1.9.3
- [Qemu-devel] [PATCH v3 31/32] ahci: Add test_hba_enable to ahci-test., (continued)
- [Qemu-devel] [PATCH v3 31/32] ahci: Add test_hba_enable to ahci-test., John Snow, 2014/08/13
- [Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50., John Snow, 2014/08/13
- [Qemu-devel] [PATCH v3 30/32] ahci: Add test_hba_spec to ahci-test., John Snow, 2014/08/13
- [Qemu-devel] [PATCH v3 27/32] ahci: Add test_pci_spec to ahci-test., John Snow, 2014/08/13
- [Qemu-devel] [PATCH v3 28/32] ahci: add test_pci_enable to ahci-test.,
John Snow <=
- [Qemu-devel] [PATCH v3 29/32] ahci: properly shadow the TFD register, John Snow, 2014/08/13