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[Qemu-devel] [PATCH 3/6] target-ppc: Optimize rlwnm MB=0 ME=31
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 3/6] target-ppc: Optimize rlwnm MB=0 ME=31 |
Date: |
Mon, 25 Aug 2014 14:25:41 -0500 |
Optimize the special case of rlwnm where MB=0 and ME=31. This can
be implemented using a ROTL.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 56 +++++++++++++++++++++++++++++------------------
1 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 889e37d..57cb381 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1721,37 +1721,49 @@ static void gen_rlwinm(DisasContext *ctx)
static void gen_rlwnm(DisasContext *ctx)
{
uint32_t mb, me;
- TCGv t0;
-#if defined(TARGET_PPC64)
- TCGv t1;
-#endif
-
mb = MB(ctx->opcode);
me = ME(ctx->opcode);
- t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
+
+ if (likely(mb == 0 && me == 31)) {
+ TCGv_i32 t0, t1;
+ t0 = tcg_temp_new_i32();
+ t1 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_andi_i32(t0, t0, 0x1f);
+ tcg_gen_rotl_i32(t1, t1, t0);
+ tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ } else {
+ TCGv t0;
#if defined(TARGET_PPC64)
- t1 = tcg_temp_new_i64();
- tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], 32, 32);
- tcg_gen_rotl_i64(t0, t1, t0);
- tcg_temp_free_i64(t1);
-#else
- tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
+ TCGv t1;
#endif
- if (unlikely(mb != 0 || me != 31)) {
+
+ t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
#if defined(TARGET_PPC64)
- mb += 32;
- me += 32;
+ t1 = tcg_temp_new_i64();
+ tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
+ cpu_gpr[rS(ctx->opcode)], 32, 32);
+ tcg_gen_rotl_i64(t0, t1, t0);
+ tcg_temp_free_i64(t1);
+#else
+ tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
#endif
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- } else {
+ if (unlikely(mb != 0 || me != 31)) {
#if defined(TARGET_PPC64)
- tcg_gen_andi_tl(t0, t0, MASK(32, 63));
+ mb += 32;
+ me += 32;
#endif
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
+ tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
+ } else {
+ tcg_gen_andi_tl(t0, t0, MASK(32, 63));
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
+ }
+ tcg_temp_free(t0);
}
- tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
--
1.7.1
- [Qemu-devel] [PATCH 0/6] target-ppc: More Cleanup of FXU Instructions, Tom Musta, 2014/08/25
- [Qemu-devel] [PATCH 1/6] target-ppc: Special Case of rlwimi Should Use Deposit, Tom Musta, 2014/08/25
- [Qemu-devel] [PATCH 2/6] target-ppc: Optimize rlwinm MB=0 ME=31, Tom Musta, 2014/08/25
- [Qemu-devel] [PATCH 3/6] target-ppc: Optimize rlwnm MB=0 ME=31,
Tom Musta <=
- [Qemu-devel] [PATCH 5/6] target-ppc: Clean up mullwo, Tom Musta, 2014/08/25
- [Qemu-devel] [PATCH 4/6] target-ppc: Clean Up mullw, Tom Musta, 2014/08/25
- [Qemu-devel] [PATCH 6/6] target-ppc: Implement mulldo with TCG, Tom Musta, 2014/08/25
- Re: [Qemu-devel] [PATCH 0/6] target-ppc: More Cleanup of FXU Instructions, Richard Henderson, 2014/08/25