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[Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs |
Date: |
Fri, 29 Aug 2014 15:37:14 +0100 |
Commit 2c7ffc414 added support for honouring the CPACR coprocessor
access control register bits which may disable access to VFP
and Neon instructions. However it failed to account for the
fact that the CPACR is only present starting from the ARMv6
architecture version, so it accidentally disabled VFP completely
for ARMv5 CPUs like the ARM926. Linux would detect this as
"no VFP present" and probably fall back to its own emulation,
but other guest OSes might crash or misbehave.
This fixes bug LP:1359930.
Reported-by: Jakub Jermar <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 8098b8d..659b104 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1255,7 +1255,14 @@ static inline bool arm_singlestep_active(CPUARMState
*env)
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
- int fpen = extract32(env->cp15.c1_coproc, 20, 2);
+ int fpen;
+
+ if (arm_feature(env, ARM_FEATURE_V6)) {
+ fpen = extract32(env->cp15.c1_coproc, 20, 2);
+ } else {
+ /* CPACR doesn't exist before v6, so VFP is always accessible */
+ fpen = 3;
+ }
if (is_a64(env)) {
*pc = env->pc;
--
1.9.1
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 14/16] target-arm: Implement pmccntr_sync function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 16/16] target-arm: Implement pmccfiltr_write function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 12/16] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 01/16] disas/libvixl: Update to upstream VIXL 1.5, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update(), Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs,
Peter Maydell <=
- [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 08/16] aarch64: raise max_cpus to 8, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 05/16] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 15/16] target-arm: Remove old code and replace with new functions, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 06/16] arm_gic: Do not force PPIs to edge-triggered mode, Peter Maydell, 2014/08/29
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2014/08/29