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Re: [Qemu-devel] [PATCH v2 0/5] ARM: add PSCI 0.2 support in TCG mode


From: Ard Biesheuvel
Subject: Re: [Qemu-devel] [PATCH v2 0/5] ARM: add PSCI 0.2 support in TCG mode
Date: Mon, 1 Sep 2014 18:01:37 +0200

On 1 September 2014 15:50, Peter Maydell <address@hidden> wrote:
> On 1 September 2014 12:55, Ard Biesheuvel <address@hidden> wrote:
>> Currently, booting multiple cores under TCG is unstable, so the restriction
>> to 1 cpu in TCG mode is retained for now. However, PSCI reset and poweroff 
>> are
>> supported.
>
> This is worrying, incidentally. What's the instability? Last time I
> tried Rob's patchset it seemed OK to me...
>

Rob seemed to be aware of this when I brought it up the other day:
my 3.17 kernel seems to boot fine, brings up the secondaries, and I
can look at /proc/interrupts or /proc/cpuinfo and see 4 CPUs, all
taking interrupts.
However, as soon as i run dmesg, i get ~50 lines of output and then
the console hangs solid. Attaching GDB reveals that the kernel is
still running, i.e., cpu_do_idle() etc, so it might just be the UART
being in a funny state


-- 
Ard.



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