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Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruct
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs |
Date: |
Thu, 11 Sep 2014 07:30:10 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 9/10/2014 5:43 PM, Pierre Mallard wrote:
> On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <address@hidden
> <mailto:address@hidden>> wrote:
>
>
> (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer
> Conversion instructions.
>
>
> There is also fcfids and fcfidus which leads to 8 instructions (fcfid,
> fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this right ?
You are correct.
>
>
> (2) Defined a new flag for FP Signed Doubleword Conversion instructions
> (PPC2_FP_CVT_S64). Use this flag exclusively when defining the opcode
> tables, e.g.
>
> +/* fctidz */
> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
>
> I'm not sure, I did understand correctly that one, indeed to have the flag
> check I have to make changes for each of the three instructions (fcfid,
> fctif, fctidz) at 2 places in translate.c :
>
> One at the gen_XXXX function definition which is quite straight forward :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
> becomes
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
>
> One in the Opcode Table which requires to use the GEN_HANDLER_E macro for the
> second type to be taken in account :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64),
> becomes
> GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64)
>
> is this right ?
Yes.
>
>
>
> (3) You would have to add the flag to all existing 64-bit CPUs that
> support floating point. And of course, to your new 440-w-fpu CPU.
>
>
> Pierre
- [Qemu-devel] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type, (continued)