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[Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3 |
Date: |
Fri, 26 Sep 2014 18:08:33 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 10 ++++++++++
target-arm/helper.c | 17 +++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4070a38..00b3ad4 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1179,6 +1179,10 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = arm_excp_target_el(cs, excp_idx);
+ /* FIXME: Use actual secure state. */
+ bool secure = false;
+ /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */
+ bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
/* Don't take exceptions if they target a lower EL. */
if (cur_el > target_el) {
@@ -1187,8 +1191,14 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
switch (excp_idx) {
case EXCP_FIQ:
+ if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) {
+ return true;
+ }
return !(env->daif & PSTATE_F);
case EXCP_IRQ:
+ if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
+ return true;
+ }
return !(env->daif & PSTATE_I)
&& (!IS_M(env) || env->regs[15] < 0xfffffff0);
default:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 161c049..c3a70d6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3656,6 +3656,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
CPUARMState *env = &cpu->env;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el;
+ /* FIXME: Use actual secure state. */
+ bool secure = false;
if (!env->aarch64) {
/* TODO: Add EL2 and 3 exception handling for AArch32. */
@@ -3670,6 +3672,21 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
case EXCP_SMC:
target_el = 3;
break;
+ case EXCP_FIQ:
+ case EXCP_IRQ:
+ {
+ const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
+ const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
+
+ target_el = 1;
+ if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
+ target_el = 2;
+ }
+ if (env->cp15.scr_el3 & scr_mask) {
+ target_el = 3;
+ }
+ break;
+ }
default:
target_el = MAX(cur_el, 1);
break;
--
1.9.1
- [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 05/11] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 06/11] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 07/11] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 03/11] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 09/11] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/26
- Re: [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model, Peter Maydell, 2014/09/26