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[Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked |
Date: |
Tue, 30 Sep 2014 16:49:42 -0500 |
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1fa9e0d..7a8eaef 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -311,6 +311,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
+ uint64_t mair_el3;
union { /* vector base address register */
struct {
uint64_t _unused_vbar;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8543813..e91a019 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -958,11 +958,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
*/
{ .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
+ .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.mair_el3),
+ offsetoflow32(CPUARMState, cp15.mair_el1) },
.resetfn = arm_cp_reset_ignore },
{ .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
+ .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.mair_el3),
+ offsetofhigh32(CPUARMState, cp15.mair_el1) },
.resetfn = arm_cp_reset_ignore },
{ .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
--
1.8.3.2
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, (continued)
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 26/33] target-arm: make DFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 31/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/09/30