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[Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit add
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit address wrapping |
Date: |
Wed, 15 Oct 2014 10:54:03 +0100 |
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
---
target-mips/cpu.h | 18 ++++++++++++++----
target-mips/translate.c | 6 +-----
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8b9a92e..51a8331 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -450,7 +450,7 @@ struct CPUMIPSState {
and RSQRT.D. */
#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
-#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
+#define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
#define MIPS_HFLAG_M16_SHIFT 10
/* If translation is interrupted between the branch instruction and
@@ -725,7 +725,7 @@ static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
- MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
+ MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
@@ -737,8 +737,18 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_64;
}
- if (env->CP0_Status & (1 << CP0St_UX)) {
- env->hflags |= MIPS_HFLAG_UX;
+
+ if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
+ !(env->CP0_Status & (1 << CP0St_UX))) {
+ env->hflags |= MIPS_HFLAG_AWRAP;
+ } else if (env->insn_flags & ISA_MIPS32R6) {
+ /* Address wrapping for Supervisor and Kernel is specified in R6 */
+ if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
+ !(env->CP0_Status & (1 << CP0St_SX))) ||
+ (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
+ !(env->CP0_Status & (1 << CP0St_KX)))) {
+ env->hflags |= MIPS_HFLAG_AWRAP;
+ }
}
#endif
if ((env->CP0_Status & (1 << CP0St_CU0)) ||
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 34d63ea..7420485 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1383,11 +1383,7 @@ static inline void gen_op_addr_add (DisasContext *ctx,
TCGv ret, TCGv arg0, TCGv
tcg_gen_add_tl(ret, arg0, arg1);
#if defined(TARGET_MIPS64)
- /* For compatibility with 32-bit code, data reference in user mode
- with Status_UX = 0 should be casted to 32-bit and sign extended.
- See the MIPS64 PRA manual, section 4.10. */
- if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
- !(ctx->hflags & MIPS_HFLAG_UX)) {
+ if (ctx->hflags & MIPS_HFLAG_AWRAP) {
tcg_gen_ext32s_i64(ret, ret);
}
#endif
--
2.1.0
- [Qemu-devel] [PULL 00/28] target-mips queue, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 01/28] target-mips: define ISA_MIPS64R6, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 02/28] target-mips: signal RI Exception on instructions removed in R6, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 03/28] target-mips: add SELEQZ and SELNEZ instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 04/28] target-mips: move LL and SC instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 05/28] target-mips: extract decode_opc_special* from decode_opc, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 06/28] target-mips: split decode_opc_special* into *_r6 and *_legacy, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 07/28] target-mips: signal RI Exception on DSP and Loongson instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit address wrapping,
Leon Alrae <=
- [Qemu-devel] [PULL 08/28] target-mips: move PREF, CACHE, LLD and SCD instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 09/28] target-mips: redefine Integer Multiply and Divide instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 10/28] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 12/28] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 15/28] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 18/28] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 17/28] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15