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[Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_s
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX |
Date: |
Wed, 15 Oct 2014 10:54:20 +0100 |
From: Peter Maydell <address@hidden>
Remove the functions gen_load_ACX and gen_store_ACX, which appear to have
been unused since they were first introduced many years ago. These functions
were the only places using the cpu_ACX[] array of TCG globals, so remove
that and its accompanying regnames_ACX[] as well.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c23cb94..446eb8a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1104,7 +1104,7 @@ enum {
/* global register indices */
static TCGv_ptr cpu_env;
static TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
+static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget, bcond;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -1195,10 +1195,6 @@ static const char * const regnames_LO[] = {
"LO0", "LO1", "LO2", "LO3",
};
-static const char * const regnames_ACX[] = {
- "ACX0", "ACX1", "ACX2", "ACX3",
-};
-
static const char * const fregnames[] = {
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
@@ -1241,17 +1237,6 @@ static inline void gen_store_gpr (TCGv t, int reg)
tcg_gen_mov_tl(cpu_gpr[reg], t);
}
-/* Moves to/from ACX register. */
-static inline void gen_load_ACX (TCGv t, int reg)
-{
- tcg_gen_mov_tl(t, cpu_ACX[reg]);
-}
-
-static inline void gen_store_ACX (TCGv t, int reg)
-{
- tcg_gen_mov_tl(cpu_ACX[reg], t);
-}
-
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr (int from, int to)
{
@@ -17716,9 +17701,6 @@ void mips_tcg_init(void)
cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
- cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUMIPSState,
active_tc.ACX[i]),
- regnames_ACX[i]);
}
cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUMIPSState,
active_tc.DSPControl),
--
2.1.0
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, (continued)
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX,
Leon Alrae <=
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/16
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/22