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[Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function |
Date: |
Tue, 21 Oct 2014 11:55:14 -0500 |
From: Fabian Aggeler <address@hidden>
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
==========
v6 -> v7
- Fix arm_is_secure comment
v5 -> v6
- Broaden CONFIG_USER conditional
- Merge resulting false returns with common comment
- Globally change Aarch# to AArch#
- Replace direct access of env->aarch64 with is_a64()
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e0e3f9b..44ed6fe 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -753,6 +753,53 @@ static inline int arm_feature(CPUARMState *env, int
feature)
return (env->features & (1ULL << feature)) != 0;
}
+#if !defined(CONFIG_USER_ONLY)
+/* Return true if exception levels below EL3 are in secure state,
+ * or would be following an exception return to that level.
+ * Unlike arm_is_secure() (which is always a question about the
+ * _current_ state of the CPU) this doesn't care about the current
+ * EL or mode.
+ */
+static inline bool arm_is_secure_below_el3(CPUARMState *env)
+{
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ return !(env->cp15.scr_el3 & SCR_NS);
+ } else {
+ /* If EL2 is not supported then the secure state is implementation
+ * defined, in which case QEMU defaults to non-secure.
+ */
+ return false;
+ }
+}
+
+/* Return true if the processor is in secure state */
+static inline bool arm_is_secure(CPUARMState *env)
+{
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
+ /* CPU currently in AArch64 state and EL3 */
+ return true;
+ } else if (!is_a64(env) &&
+ (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
+ /* CPU currently in AArch32 state and monitor mode */
+ return true;
+ }
+ }
+ return arm_is_secure_below_el3(env);
+}
+
+#else
+static inline bool arm_is_secure_below_el3(CPUARMState *env)
+{
+ return false;
+}
+
+static inline bool arm_is_secure(CPUARMState *env)
+{
+ return false;
+}
+#endif
+
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
--
1.8.3.2
- [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 03/32] target-arm: reject switching to monitor mode, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function,
Greg Bellows <=
- [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 10/32] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking, Greg Bellows, 2014/10/21