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[Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition |
Date: |
Tue, 21 Oct 2014 11:55:30 -0500 |
From: Sergey Fedorov <address@hidden>
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f9221a4..2202465 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -181,6 +181,7 @@ typedef struct CPUARMState {
uint64_t c1_sys; /* System control register. */
uint64_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
+ uint32_t c1_sder; /* Secure debug enable register. */
uint32_t c1_nsacr; /* Non-secure access control register. */
uint64_t ttbr0_el1; /* MMU translation table base 0. */
uint64_t ttbr1_el1; /* MMU translation table base 1. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f12181f..af62074 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2409,6 +2409,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = {
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.resetvalue = 0, .writefn = scr_write},
+ { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
.access = PL3_RW | PL1_R, .resetvalue = 0,
.writefn = nsacr_write, .readfn = nsacr_read,
--
1.8.3.2
- [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el, (continued)
- [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition,
Greg Bellows <=
- [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 23/32] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 29/32] target-arm: make PAR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/10/21