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[Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes |
Date: |
Fri, 24 Oct 2014 12:37:15 +0100 |
From: Rob Herring <address@hidden>
User mode emulation should never get interrupts and thus should not
use the system emulation exception handler function. Remove the reference,
and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add
system mode only functionality to it.
Signed-off-by: Rob Herring <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/cpu.c | 2 +-
target-arm/cpu64.c | 2 ++
target-arm/helper-a64.c | 3 +++
target-arm/helper.c | 5 -----
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 67cd176..2061cb7 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1109,7 +1109,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->do_interrupt = arm_cpu_do_interrupt;
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
@@ -1118,6 +1117,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
#ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
#else
+ cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_arm_cpu;
#endif
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index c30f47e..a95367a 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -196,7 +196,9 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
{
CPUClass *cc = CPU_CLASS(oc);
+#if !defined(CONFIG_USER_ONLY)
cc->do_interrupt = aarch64_cpu_do_interrupt;
+#endif
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 8228e29..7ae84f6 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -438,6 +438,8 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val,
uint32_t bytes)
return crc32c(acc, buf, bytes) ^ 0xffffffff;
}
+#if !defined(CONFIG_USER_ONLY)
+
/* Handle a CPU exception. */
void aarch64_cpu_do_interrupt(CPUState *cs)
{
@@ -518,3 +520,4 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->pc = addr;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
+#endif
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2669e15..497178a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3644,11 +3644,6 @@ uint32_t HELPER(rbit)(uint32_t x)
#if defined(CONFIG_USER_ONLY)
-void arm_cpu_do_interrupt(CPUState *cs)
-{
- cs->exception_index = -1;
-}
-
int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
--
1.9.1
- [Qemu-devel] [PULL 00/23] target-arm queue, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any", Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes,
Peter Maydell <=
- [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter., Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 06/23] disas/libvixl/a64/instructions-a64.h: Remove unused constants, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 23/23] target-arm: A32: Emulate the SMC instruction, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function, Peter Maydell, 2014/10/24