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Re: [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking

From: Greg Bellows
Subject: Re: [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking
Date: Mon, 27 Oct 2014 10:59:58 -0500

On 27 October 2014 06:57, Peter Maydell <address@hidden> wrote:
On 26 October 2014 22:30, Peter Maydell <address@hidden> wrote:
> In fact, since all of the "exception is not taken" cases are for
> "we are in secure EL3 and the exception is not being routed to
> secure EL3" you could just make all those entries read "1" and
> rely on the "target_el < current_el" check. That does slightly
> harm readability though.

Thinking further about this I actually prefer it -- it completely
separates routing from masking. So you should make those entries
read '1' and then just use -1 for "not possible" (and assert
that the table lookup never gives you -1).

> I looked through the tables for the AArch32 routing, and I can't
> see anywhere where they're different from the AArch64 routing
> handling. [...] Did I miss something?

I did! If EL3 is AArch32 and the SCR.FIQ etc bits are clear then
the FIQ/IRQ in the secure world target EL3, not EL1 (since the
latter doesn't exist). We can handle that by using the AArch64 table
anyway and just having a bit at the end that says "if we're secure
and target_el is 1 then set it to 3", or if you prefer with a second

Right, this is what I was saying about either needing another column or or table.  If we are going with the table approach I think we should go all the way and not add a "conditional".  Besides, the tables are small anyway.  I extended the existing able to take 32/64 bit identifier.

The changes discussed above will be made in v8.
-- PMM

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