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[Qemu-devel] [PATCH v8 27/27] target-arm: add cpu feature EL3 to CPUs wi
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v8 27/27] target-arm: add cpu feature EL3 to CPUs with Security Extensions |
Date: |
Thu, 30 Oct 2014 16:28:58 -0500 |
From: Fabian Aggeler <address@hidden>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a711834..d76b47e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -610,6 +610,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -696,6 +697,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -763,6 +765,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -830,6 +833,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
- [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register, (continued)
- [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 23/27] target-arm: make PAR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 20/27] target-arm: make IFSR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 11/27] target-arm: add SDER definition, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 27/27] target-arm: add cpu feature EL3 to CPUs with Security Extensions,
Greg Bellows <=
- [Qemu-devel] [PATCH v8 08/27] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 15/27] target-arm: make CSSELR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 07/27] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/10/31