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[Qemu-devel] [PULL 06/34] target-mips: add new Read-Inhibit and Execute-
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 06/34] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions |
Date: |
Mon, 3 Nov 2014 16:11:20 +0000 |
An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain XIE bit.
An Read-Inhibit exception occurs when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
---
target-mips/cpu.h | 5 ++++-
target-mips/helper.c | 25 ++++++++++++++++++++++++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 38f90f2..a9e1bc2 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -247,6 +247,7 @@ struct CPUMIPSState {
int32_t CP0_PageGrain;
#define CP0PG_RIE 31
#define CP0PG_XIE 30
+#define CP0PG_IEC 27
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
@@ -646,8 +647,10 @@ enum {
EXCP_C2E,
EXCP_CACHE, /* 32 */
EXCP_DSPDIS,
+ EXCP_TLBXI,
+ EXCP_TLBRI,
- EXCP_LAST = EXCP_DSPDIS,
+ EXCP_LAST = EXCP_TLBRI,
};
/* Dummy exception for conditional stores. */
#define EXCP_SC 0x100
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 49187a3..37038ef 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -273,7 +273,22 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
/* TLB match but 'D' bit is cleared */
exception = EXCP_LTLBL;
break;
-
+ case TLBRET_XI:
+ /* Execute-Inhibit Exception */
+ if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
+ exception = EXCP_TLBXI;
+ } else {
+ exception = EXCP_TLBL;
+ }
+ break;
+ case TLBRET_RI:
+ /* Read-Inhibit Exception */
+ if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
+ exception = EXCP_TLBRI;
+ } else {
+ exception = EXCP_TLBL;
+ }
+ break;
}
/* Raise exception */
env->CP0_BadVAddr = address;
@@ -404,6 +419,8 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_MDMX] = "MDMX",
[EXCP_C2E] = "precise coprocessor 2",
[EXCP_CACHE] = "cache error",
+ [EXCP_TLBXI] = "TLB execute-inhibit",
+ [EXCP_TLBRI] = "TLB read-inhibit",
};
target_ulong exception_resume_pc (CPUMIPSState *env)
@@ -622,6 +639,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_C2E:
cause = 18;
goto set_EPC;
+ case EXCP_TLBRI:
+ cause = 19;
+ goto set_EPC;
+ case EXCP_TLBXI:
+ cause = 20;
+ goto set_EPC;
case EXCP_MDMX:
cause = 22;
goto set_EPC;
--
2.1.0
- [Qemu-devel] [PULL 00/34] target-mips queue, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 01/34] target-mips: add KScratch registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 03/34] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 02/34] softmmu: provide softmmu access type enum, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 06/34] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions,
Leon Alrae <=
- [Qemu-devel] [PULL 04/34] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 05/34] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 12/34] target-mips: CP0_Status.CU0 no longer allows the user to access CP0, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 08/34] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 07/34] target-mips: add TLBINV support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 10/34] target-mips: add Config5.SBRI, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 11/34] target-mips: implement forbidden slot, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 13/34] target-mips: add restrictions for possible values in registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 09/34] target-mips: update cpu_save/cpu_load to support new registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 15/34] target-mips: enable features in MIPS64R6-generic CPU, Leon Alrae, 2014/11/03