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Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.D
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From: |
Maciej W. Rozycki |
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Subject: |
Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits |
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Date: |
Fri, 7 Nov 2014 12:33:26 +0000 |
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User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Fri, 7 Nov 2014, Leon Alrae wrote:
> When I've been applying this patch to my mips-next candidate branch for
> 2.2 I realized that you haven't rebased it onto the recent version where
> MSA has been added to mips32r5-generic. Now I don't think that having
> DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
> change mips32r5-generic part in your patch slightly: instead of setting
> CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.
I have been working with the current trunk, the change applies
correctly there AFAICT.
I have no objections to changing mips32r5-generic, it is artificial
anyway. But what do you mean by DSP and MSA on one CPU having no sense,
is there a conflict between the two ASEs?
Maciej