[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping |
Date: |
Fri, 7 Nov 2014 16:56:08 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Correct the way PC is updated when single-stepping instructions, by
keeping the old PC only for the BS_EXCP (exception condition) state.
Some MTC0 (and possibly other) instructions switch to the BS_STOP state
to terminate the current translation block, so that the state transition
of the simulated CPU resulting from the CP0 operation takes effect with
the following instruction. This happens with `mtc0 <reg>,c0_config' for
example, typically used to set KSEG0 cacheability.
While single-stepping this has a side-effect of not advancing the PC
past the instruction just executed; subsequent single-step traps will
stop at the same instruction repeatedly. Example:
(gdb) stepi
0x80004d24 in _start ()
5: x/i $pc
=> 0x80004d24 <_start+364>: mfc0 t1,c0_config
(gdb)
0x80004d28 in _start ()
5: x/i $pc
=> 0x80004d28 <_start+368>: li at,-8
(gdb)
0x80004d2c in _start ()
5: x/i $pc
=> 0x80004d2c <_start+372>: and t1,t1,at
(gdb)
0x80004d30 in _start ()
5: x/i $pc
=> 0x80004d30 <_start+376>: ori t1,t1,0x3
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0 t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0 t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0 t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0 t1,c0_config
(gdb)
-- oops!
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 194d4fb..0bea3c4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19112,7 +19112,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
gen_io_end();
}
if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
- save_cpu_state(&ctx, ctx.bstate == BS_NONE);
+ save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
} else {
switch (ctx.bstate) {
--
2.1.0
- [Qemu-devel] [PULL 0/7] target-mips queue, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 1/7] mips: Remove CONFIG_VT82C686 from non-Fulong configs, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping,
Leon Alrae <=
- [Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ, Leon Alrae, 2014/11/07
- Re: [Qemu-devel] [PULL 0/7] target-mips queue, Peter Maydell, 2014/11/10