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[Qemu-devel] [PULL 39/47] serial: reset thri_pending on IER writes with
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 39/47] serial: reset thri_pending on IER writes with THRI=0 |
Date: |
Mon, 15 Dec 2014 17:38:23 +0100 |
This is responsible for failure of migration from 2.2 to 2.1, because
thr_ipending is always one in practice.
serial.c is setting thr_ipending unconditionally. However, thr_ipending
is not used at all if THRI=0, and it will be overwritten again the next
time THRE or THRI changes. For that reason, we can set thr_ipending to
zero every time THRI is reset.
There is disagreement on whether LSR.THRE should be resampled when IER.THRI
goes from 1 to 1. This patch does not touch the code, leaving that for
QEMU 2.3+.
This has no semantic change and is enough to fix migration in the common
case where the interrupt is not pending or is reported in IIR. It does not
change the migration format, so 2.2.0 -> 2.1 will remain broken but we
can fix 2.2.1 -> 2.1 without breaking 2.2.1 <-> 2.2.0.
The case that remains broken (the one in which the subsection is strictly
necessary) is when THRE=1, the THRI interrupt has *not* been acknowledged
yet, and a higher-priority interrupt comes. In this case, you need the
subsection to tell the source that the lower-priority THRI interrupt is
pending. The subsection's breakage of migration, in this case, prevents
continuing the VM on the destination with an invalid state.
Cc: address@hidden
Reported-by: Igor Mammedov <address@hidden>
Reviewed-by: Dr. David Alan Gilbert <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/char/serial.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/hw/char/serial.c b/hw/char/serial.c
index ebcacdc..8c42d03 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -350,10 +350,24 @@ static void serial_ioport_write(void *opaque, hwaddr
addr, uint64_t val,
s->poll_msl = 0;
}
}
- if (s->lsr & UART_LSR_THRE) {
+
+ /* Turning on the THRE interrupt on IER can trigger the interrupt
+ * if LSR.THRE=1, even if it had been masked before by reading IIR.
+ * This is not in the datasheet, but Windows relies on it. It is
+ * unclear if THRE has to be resampled every time THRI becomes
+ * 1, or only on the rising edge. Bochs does the latter, and
Windows
+ * always toggles IER to all zeroes and back to all ones. But for
+ * now leave it as it has always been in QEMU.
+ *
+ * If IER.THRI is zero, thr_ipending is not used. Set it to zero
+ * so that the thr_ipending subsection is not migrated.
+ */
+ if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
s->thr_ipending = 1;
- serial_update_irq(s);
+ } else {
+ s->thr_ipending = 0;
}
+ serial_update_irq(s);
}
break;
case 2:
--
1.8.3.1
- [Qemu-devel] [PULL 29/47] cpu-exec: invalidate nocache translation if they are interrupted, (continued)
- [Qemu-devel] [PULL 29/47] cpu-exec: invalidate nocache translation if they are interrupted, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 30/47] timer: introduce new QEMU_CLOCK_VIRTUAL_RT clock, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 31/47] cpus: make icount warp behave well with respect to stop/cont, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 32/47] i386: do not cross the pages boundaries in replay mode, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 34/47] target-i386: add VME to all CPUs, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 33/47] pc: add 2.3 machine types, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 35/47] target-i386: add f16c and rdrand to Haswell and Broadwell, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 36/47] target-i386: add Ivy Bridge CPU model, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 38/47] linuxboot: fix loading old kernels, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 37/47] kvm/apic: fix 2.2->2.1 migration, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 39/47] serial: reset thri_pending on IER writes with THRI=0,
Paolo Bonzini <=
- [Qemu-devel] [PULL 40/47] serial: clean up THRE/TEMT handling, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 42/47] serial: only resample THR interrupt on rising edge of IER.THRI, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 41/47] serial: update LSR on enabling/disabling FIFOs, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 43/47] sdhci: Set a default frequency clock, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 44/47] sdhci: Remove class "virtual" methods, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 45/47] sdhci: Add "sysbus" to sdhci QOM types and methods, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 46/47] sdhci: Define SDHCI PCI ids, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 47/47] sdhci: Support SDHCI devices on PCI, Paolo Bonzini, 2014/12/15
- Re: [Qemu-devel] [PULL 00/47] Patches for KVM, x86, SCSI, migration fixes (2014-12-15), Peter Maydell, 2014/12/16