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Re: [Qemu-devel] [PATCH v7 2/7] stm32f2xx_USART: Add the stm32f2xx USART
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v7 2/7] stm32f2xx_USART: Add the stm32f2xx USART Controller |
Date: |
Mon, 15 Dec 2014 21:47:24 -0800 |
On Wed, Dec 10, 2014 at 12:46 AM, Alistair Francis <address@hidden> wrote:
> This patch adds the stm32f2xx USART controller
> (UART also uses the same controller).
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> V6:
> - Rename to STM32F2XX
> - Fix up unimplemented printing
> - Add a qemu_chr_accept()
> V3:
> - Update debug printing
> V2:
> - Drop charecters if the device is not enabled
> - Thanks to Peter C
>
> default-configs/arm-softmmu.mak | 1 +
> hw/char/Makefile.objs | 1 +
> hw/char/stm32f2xx_usart.c | 219
> ++++++++++++++++++++++++++++++++++++++
> include/hw/char/stm32f2xx_usart.h | 69 ++++++++++++
> 4 files changed, 290 insertions(+)
> create mode 100644 hw/char/stm32f2xx_usart.c
> create mode 100644 include/hw/char/stm32f2xx_usart.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index faea100..1348104 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -79,6 +79,7 @@ CONFIG_REALVIEW=y
> CONFIG_ZAURUS=y
> CONFIG_ZYNQ=y
> CONFIG_STM32F2XX_TIMER=y
> +CONFIG_STM32F2XX_USART=y
>
> CONFIG_VERSATILE_PCI=y
> CONFIG_VERSATILE_I2C=y
> diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
> index 317385d..5931cc8 100644
> --- a/hw/char/Makefile.objs
> +++ b/hw/char/Makefile.objs
> @@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
> obj-$(CONFIG_SH4) += sh_serial.o
> obj-$(CONFIG_PSERIES) += spapr_vty.o
> obj-$(CONFIG_DIGIC) += digic-uart.o
> +obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
>
> common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
> common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
> diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
> new file mode 100644
> index 0000000..843ff4a
> --- /dev/null
> +++ b/hw/char/stm32f2xx_usart.c
> @@ -0,0 +1,219 @@
> +/*
> + * STM32F2XX USART
> + *
> + * Copyright (c) 2014 Alistair Francis <address@hidden>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/char/stm32f2xx_usart.h"
> +
> +#ifndef STM_USART_ERR_DEBUG
> +#define STM_USART_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (STM_USART_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static int stm32f2xx_usart_can_receive(void *opaque)
> +{
> + STM32F2XXUsartState *s = opaque;
> +
> + if (!(s->usart_sr & USART_SR_RXNE)) {
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int
> size)
> +{
> + STM32F2XXUsartState *s = opaque;
> +
> + s->usart_dr = *buf;
> +
> + if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
> + /* USART not enabled - drop the chars */
> + DB_PRINT("Dropping the chars\n");
> + return;
> + }
> +
> + s->usart_sr |= USART_SR_RXNE;
> +
> + if (s->usart_cr1 & USART_CR1_RXNEIE) {
> + qemu_set_irq(s->irq, 1);
> + }
> +
> + DB_PRINT("Receiving: %c\n", s->usart_dr);
> +}
> +
> +static void stm32f2xx_usart_reset(DeviceState *dev)
> +{
> + STM32F2XXUsartState *s = STM32F2XX_USART(dev);
> +
> + s->usart_sr = USART_SR_RESET;
> + s->usart_dr = 0x00000000;
> + s->usart_brr = 0x00000000;
> + s->usart_cr1 = 0x00000000;
> + s->usart_cr2 = 0x00000000;
> + s->usart_cr3 = 0x00000000;
> + s->usart_gtpr = 0x00000000;
Does the interrupt lower on a reset?
> +}
> +
> +static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + STM32F2XXUsartState *s = opaque;
> + uint64_t retvalue;
> +
> + DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
> +
> + switch (addr) {
> + case USART_SR:
> + retvalue = s->usart_sr;
> + s->usart_sr &= ~USART_SR_TC;
> + if (s->chr) {
> + qemu_chr_accept_input(s->chr);
> + }
> + return retvalue;
> + case USART_DR:
> + DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char)
> s->usart_dr);
> + s->usart_sr |= USART_SR_TXE;
How does a read of the data register affect the TX data-path?
> + s->usart_sr &= ~USART_SR_RXNE;
> + if (s->chr) {
> + qemu_chr_accept_input(s->chr);
> + }
> + return s->usart_dr & 0x3FF;
> + case USART_BRR:
> + return s->usart_brr;
> + case USART_CR1:
> + return s->usart_cr1;
> + case USART_CR2:
> + return s->usart_cr2;
> + case USART_CR3:
> + return s->usart_cr3;
> + case USART_GTPR:
> + return s->usart_gtpr;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> + return 0;
> + }
> +
> + return 0;
> +}
> +
> +static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + STM32F2XXUsartState *s = opaque;
> + uint32_t value = val64;
> + unsigned char ch;
> +
> + DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
> +
> + switch (addr) {
> + case USART_SR:
> + if (value <= 0x3FF) {
> + s->usart_sr = value;
> + } else {
> + s->usart_sr &= value;
> + }
If you set the interrupt enable bit before RXNE is cleared, should the
interrupt raise here?
Regards,
Peter
> + return;
> + case USART_DR:
> + if (value < 0xF000) {
> + ch = value;
> + if (s->chr) {
> + qemu_chr_fe_write_all(s->chr, &ch, 1);
> + }
> + s->usart_sr |= USART_SR_TC;
> + s->usart_sr &= ~USART_SR_TXE;
> + }
> + return;
> + case USART_BRR:
> + s->usart_brr = value;
> + return;
> + case USART_CR1:
> + s->usart_cr1 = value;
> + return;
> + case USART_CR2:
> + s->usart_cr2 = value;
> + return;
> + case USART_CR3:
> + s->usart_cr3 = value;
> + return;
> + case USART_GTPR:
> + s->usart_gtpr = value;
> + return;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> + }
> +}
> +
> +static const MemoryRegionOps stm32f2xx_usart_ops = {
> + .read = stm32f2xx_usart_read,
> + .write = stm32f2xx_usart_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void stm32f2xx_usart_init(Object *obj)
> +{
> + STM32F2XXUsartState *s = STM32F2XX_USART(obj);
> +
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
> +
> + memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
> + TYPE_STM32F2XX_USART, 0x2000);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
> +
> + s->chr = qemu_char_get_next_serial();
> +
> + if (s->chr) {
> + qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
> + stm32f2xx_usart_receive, NULL, s);
> + }
> +}
> +
> +static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = stm32f2xx_usart_reset;
> +}
> +
> +static const TypeInfo stm32f2xx_usart_info = {
> + .name = TYPE_STM32F2XX_USART,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(STM32F2XXUsartState),
> + .instance_init = stm32f2xx_usart_init,
> + .class_init = stm32f2xx_usart_class_init,
> +};
> +
> +static void stm32f2xx_usart_register_types(void)
> +{
> + type_register_static(&stm32f2xx_usart_info);
> +}
> +
> +type_init(stm32f2xx_usart_register_types)
> diff --git a/include/hw/char/stm32f2xx_usart.h
> b/include/hw/char/stm32f2xx_usart.h
> new file mode 100644
> index 0000000..c9fad3c
> --- /dev/null
> +++ b/include/hw/char/stm32f2xx_usart.h
> @@ -0,0 +1,69 @@
> +/*
> + * STM32F2XX USART
> + *
> + * Copyright (c) 2014 Alistair Francis <address@hidden>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/sysbus.h"
> +#include "sysemu/char.h"
> +#include "hw/hw.h"
> +
> +#define USART_SR 0x00
> +#define USART_DR 0x04
> +#define USART_BRR 0x08
> +#define USART_CR1 0x0C
> +#define USART_CR2 0x10
> +#define USART_CR3 0x14
> +#define USART_GTPR 0x18
> +
> +#define USART_SR_RESET 0x00C00000
> +
> +#define USART_SR_TXE (1 << 7)
> +#define USART_SR_TC (1 << 6)
> +#define USART_SR_RXNE (1 << 5)
> +
> +#define USART_CR1_UE (1 << 13)
> +#define USART_CR1_RXNEIE (1 << 5)
> +#define USART_CR1_TE (1 << 3)
> +#define USART_CR1_RE (1 << 2)
> +
> +#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
> +#define STM32F2XX_USART(obj) \
> + OBJECT_CHECK(STM32F2XXUsartState, (obj), TYPE_STM32F2XX_USART)
> +
> +typedef struct {
> + /* <private> */
> + SysBusDevice parent_obj;
> +
> + /* <public> */
> + MemoryRegion mmio;
> +
> + uint32_t usart_sr;
> + uint32_t usart_dr;
> + uint32_t usart_brr;
> + uint32_t usart_cr1;
> + uint32_t usart_cr2;
> + uint32_t usart_cr3;
> + uint32_t usart_gtpr;
> +
> + CharDriverState *chr;
> + qemu_irq irq;
> +} STM32F2XXUsartState;
> --
> 2.1.0
>
>
- [Qemu-devel] [PATCH v7 0/7] Netduino 2 Machine Model, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 1/7] stm32f2xx_timer: Add the stm32f2xx Timer, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 2/7] stm32f2xx_USART: Add the stm32f2xx USART Controller, Alistair Francis, 2014/12/10
- Re: [Qemu-devel] [PATCH v7 2/7] stm32f2xx_USART: Add the stm32f2xx USART Controller,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v7 3/7] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 4/7] target_arm: Remove memory region init from armv7m_init, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 5/7] target_arm: Parameterise the irq lines for armv7m_init, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 6/7] stm32f205: Add the stm32f205 SoC, Alistair Francis, 2014/12/10
- [Qemu-devel] [PATCH v7 7/7] netduino2: Add the Netduino 2 Machine, Alistair Francis, 2014/12/10
- Re: [Qemu-devel] [PATCH v7 0/7] Netduino 2 Machine Model, Peter Maydell, 2014/12/15