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[Qemu-devel] [PULL 24/30] target-mips: Add missing calls to synchronise
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 24/30] target-mips: Add missing calls to synchronise SoftFloat status |
Date: |
Tue, 16 Dec 2014 19:49:10 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Add missing calls to synchronise the SoftFloat status with the CP1.FSCR:
+ for the rounding and flush-to-zero modes upon processor reset,
+ for the flush-to-zero mode on FSCR updates through the GDB stub.
Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE
macro.
Signed-off-by: Thomas Schwinge <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 12 ++++++++++++
target-mips/gdbstub.c | 8 +++-----
target-mips/op_helper.c | 12 ------------
target-mips/translate.c | 2 ++
4 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index f8cf143..8875c97 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -777,6 +777,18 @@ target_ulong exception_resume_pc (CPUMIPSState *env);
extern unsigned int ieee_rm[];
int ieee_ex_to_mips(int xcpt);
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
+ &env->active_fpu.fp_status);
+}
+
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 2f2ffd2..9845d88 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -74,10 +74,6 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
return 0;
}
-#define RESTORE_ROUNDING_MODE \
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
- &env->active_fpu.fp_status)
-
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -95,7 +91,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
case 70:
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
/* set rounding mode */
- RESTORE_ROUNDING_MODE;
+ restore_rounding_mode(env);
+ /* set flush-to-zero mode */
+ restore_flush_mode(env);
break;
case 71:
/* FIR is read-only. Ignore writes. */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7e632f6..d619ba4 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2280,18 +2280,6 @@ unsigned int ieee_rm[] = {
float_round_down
};
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
- set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
- &env->active_fpu.fp_status);
-}
-
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
target_ulong arg1 = 0;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9d90da0..571b7d7 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19617,6 +19617,8 @@ void cpu_state_reset(CPUMIPSState *env)
}
compute_hflags(env);
+ restore_rounding_mode(env);
+ restore_flush_mode(env);
cs->exception_index = EXCP_NONE;
}
--
2.1.0
- [Qemu-devel] [PULL 17/30] target-mips: Output CP0.Config2-5 in the register dump, (continued)
- [Qemu-devel] [PULL 17/30] target-mips: Output CP0.Config2-5 in the register dump, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 14/30] target-mips: Correct the handling of writes to CP0.Status for MIPSr6, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 12/30] target-mips: Restore the order of helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 16/30] target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 21/30] target-mips: gdbstub: Clean up FPU register handling, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 22/30] target-mips: Also apply the CP0.Status mask to MTTC0, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 18/30] target-mips: Fix CP0.Config3.ISAOnExc write accesses, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 19/30] target-mips: Tighten ISA level checks, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 23/30] linux-user: Use the 5KEf processor for 64-bit emulation, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 24/30] target-mips: Add missing calls to synchronise SoftFloat status,
Leon Alrae <=
- [Qemu-devel] [PULL 20/30] target-mips: Correct 32-bit address space wrapping, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 26/30] target-mips: Fix DisasContext's ulri member initialization, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 25/30] target-mips: Use local float status pointer across MSA macros, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 27/30] target-mips: convert single case switch into if statement, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 28/30] disas/mips: remove unused mips_msa_control_names_numeric[32], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 30/30] target-mips: remove excp_names[] from linux-user as it is unused, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 29/30] disas/mips: disable unused mips16_to_32_reg_map[], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 05/30] target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 07/30] target-mips: Fix formatting in `decode_extended_mips16_opc', Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 06/30] target-mips: Enable vectored interrupt support for the 74Kf CPU, Leon Alrae, 2014/12/16