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[Qemu-devel] [PULL 04/30] target-mips: Make CP0.Config4 and CP0.Config5
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 04/30] target-mips: Make CP0.Config4 and CP0.Config5 registers signed |
Date: |
Tue, 16 Dec 2014 19:48:50 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c01bbda..a08c2c8 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -446,8 +446,8 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
- uint32_t CP0_Config4;
- uint32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
#define CP0C4_IE 29
#define CP0C4_KScrExist 16
@@ -456,8 +456,8 @@ struct CPUMIPSState {
#define CP0C4_FTLBWays 4
#define CP0C4_FTLBSets 0
#define CP0C4_MMUSizeExt 0
- uint32_t CP0_Config5;
- uint32_t CP0_Config5_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
#define CP0C5_M 31
#define CP0C5_K 30
#define CP0C5_CV 29
--
2.1.0
- [Qemu-devel] [PULL 20/30] target-mips: Correct 32-bit address space wrapping, (continued)
- [Qemu-devel] [PULL 20/30] target-mips: Correct 32-bit address space wrapping, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 26/30] target-mips: Fix DisasContext's ulri member initialization, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 25/30] target-mips: Use local float status pointer across MSA macros, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 27/30] target-mips: convert single case switch into if statement, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 28/30] disas/mips: remove unused mips_msa_control_names_numeric[32], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 30/30] target-mips: remove excp_names[] from linux-user as it is unused, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 29/30] disas/mips: disable unused mips16_to_32_reg_map[], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 05/30] target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 07/30] target-mips: Fix formatting in `decode_extended_mips16_opc', Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 06/30] target-mips: Enable vectored interrupt support for the 74Kf CPU, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 04/30] target-mips: Make CP0.Config4 and CP0.Config5 registers signed,
Leon Alrae <=
- [Qemu-devel] [PULL 08/30] target-mips: Fix formatting in `mips_defs', Leon Alrae, 2014/12/16
- Re: [Qemu-devel] [PULL 00/30] target-mips queue, Peter Maydell, 2014/12/17