Re: [Qemu-devel] [PULL 05/10] tcg: Put opcodes in a linked list

[Peter Maydell]

On 9 January 2015 at 21:23, Richard Henderson <address@hidden> wrote:
> The previous setup required ops and args to be completely sequential,
> and was error prone when it came to both iteration and optimization.
>
> Signed-off-by: Richard Henderson <address@hidden>

>  void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
>  {
>      memop = tcg_canonicalize_memop(memop, 0, 0);
> -
> -    *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
> -    tcg_add_param_i32(val);
> -    tcg_add_param_tl(addr);
> -    *tcg_ctx.gen_opparam_ptr++ = memop;
> -    *tcg_ctx.gen_opparam_ptr++ = idx;
> +    gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
>  }

>  void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
> @@ -1910,7 +1932,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, 
> TCGArg idx, TCGMemOp memop)
>      memop = tcg_canonicalize_memop(memop, 1, 0);
>
>      if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
> -        tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
> +        gen_ldst_i32(INDEX_op_qemu_ld_i32, TCGV_LOW(val), addr, idx, memop);
>          if (memop & MO_SIGN) {
>              tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
>          } else {

memop and idx are the wrong way round in this call to gen_ldst_i32...

This causes "make check" to fail on a 32-bit host, because we end
up timing out on one of the ACPI tests because what should have been
an 8-bit load becomes a 32-bit one.

-- PMM