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Re: [Qemu-devel] [PATCH v2] tcg-arm: more instruction execution control

From: Andrew Jones
Subject: Re: [Qemu-devel] [PATCH v2] tcg-arm: more instruction execution control
Date: Tue, 13 Jan 2015 16:46:45 +0100
User-agent: Mutt/1.5.23 (2014-03-12)

On Mon, Jan 12, 2015 at 01:46:47PM +0100, Andrew Jones wrote:
> Cleanup XN/PXN handling in get_phys_addr_lpae, and implement all but
> EL2 support of the following ARMv8 sections
>   D4.5.1 Memory access control: Access permissions for instruction
>          execution
>   G4.7.2 Execute-never restrictions on instruction fetching
> G4.7.2 matches the ARMv7 section B3.7.2 when long-descriptors are used.
> Signed-off-by: Andrew Jones <address@hidden>

While confirming the documentation wasn't wrong (it wasn't),
I see I missed another issue with qemu's instruction execution
control. For AArch64, EL0 can execute code even if it doesn't have
R/W access, i.e. AP[1]=0. To make this fix more clear I've done it
in a separate patch, and then rebased this patch on that. Thus,
please drop this patch, as I'll send a 2-patch patch series now
that replaces it.


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