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Re: [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opc
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format |
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Date: |
Wed, 21 Jan 2015 10:16:22 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 |
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
> + case OPC2_32_RR2_MUL_32:
> + gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
> + break;
> + case OPC2_32_RR2_MUL_64:
> + gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
> + cpu_gpr_d[r2]);
> + break;
What happend to flags computation?
r~
- [Qemu-devel] [PATCH 0/4] TriCore add instructions of RR1, RR2, RRPW and RRR opcode format, Bastian Koppelmann, 2015/01/21
- [Qemu-devel] [PATCH 1/4] target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode, Bastian Koppelmann, 2015/01/21
- [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format, Bastian Koppelmann, 2015/01/21
- Re: [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format,
Richard Henderson <=
- [Qemu-devel] [PATCH 3/4] target-tricore: Add instructions of RRPW opcode format, Bastian Koppelmann, 2015/01/21
- [Qemu-devel] [PATCH 4/4] target-tricore: Add instructions of RRR opcode format, Bastian Koppelmann, 2015/01/21