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Re: [Qemu-devel] [PATCH v5 03/10] rocker: add register programming guide
From: |
Scott Feldman |
Subject: |
Re: [Qemu-devel] [PATCH v5 03/10] rocker: add register programming guide |
Date: |
Wed, 4 Feb 2015 22:29:07 -0800 |
On Mon, Feb 2, 2015 at 8:19 AM, Stefan Hajnoczi <address@hidden> wrote:
> On Thu, Jan 22, 2015 at 12:03:52AM -0800, address@hidden wrote:
>> +SECTION 7: Switch Control
>> +=========================
>> +
>> +This section covers switch-wide register settings.
>> +
>> +Control
>> +-------
>> +
>> +This register is used for low level control of the switch.
>> +
>> + CONTROL: offset 0x0300, 32-bit, (W)
>> +
>> + bit name description
>> +
>> ------------------------------------------------------------------------
>> + [0] CONTROL_RESET If set, device will perform reset
>
> This doesn't block the patch series, but I have a question:
>
> Reset is not defined.
>
> What exactly gets reset?
The internal structures for the device would get reset to a power-on
state. In rockers case, the flow tables would be cleared and the desc
rings would be reset.
>
> How does the CPU detect that the device has completed the reset
> procedure? Is this supposed to be synchronous? If yes, is that a good
> idea (i.e. hopefully resetting doesn't involve any blocking operations
> or operations that take a long time)?
Ya, in this case we want the reset to be non-blocking and synchronous.