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[Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs wh
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set. |
Date: |
Thu, 5 Feb 2015 14:02:48 +0000 |
From: Xiangyu Hu <address@hidden>
While FMULX returns a 2.0f float when two operators are infinity and
zero, those operators should be unpacked from raw inputs first. Inconsistent
cases would occur when operators are denormalized floats in flush-to-zero
mode. A wrong codepath will be entered and 2.0f will not be returned
without this patch.
Fix by checking whether inputs need to be flushed before running into
different codepaths.
Signed-off-by: Xiangyu Hu <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper-a64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 81066ca..ebd9247 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -135,6 +135,9 @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
{
float_status *fpst = fpstp;
+ a = float32_squash_input_denormal(a, fpst);
+ b = float32_squash_input_denormal(b, fpst);
+
if ((float32_is_zero(a) && float32_is_infinity(b)) ||
(float32_is_infinity(a) && float32_is_zero(b))) {
/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
@@ -148,6 +151,9 @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
{
float_status *fpst = fpstp;
+ a = float64_squash_input_denormal(a, fpst);
+ b = float64_squash_input_denormal(b, fpst);
+
if ((float64_is_zero(a) && float64_is_infinity(b)) ||
(float64_is_infinity(a) && float64_is_zero(b))) {
/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
--
1.9.1
- [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code, (continued)
- [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set.,
Peter Maydell <=
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 24/28] disas/libvixl: Update to upstream VIXL 1.7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 07/28] target-arm: Split NO_MIGRATE into ALIAS and NO_RAW, Peter Maydell, 2015/02/05
- Re: [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2015/02/05