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Re: [Qemu-devel] Intel X86 hardware transactional memory


From: Peter Maydell
Subject: Re: [Qemu-devel] Intel X86 hardware transactional memory
Date: Fri, 6 Feb 2015 08:28:18 +0000

On 5 February 2015 at 05:09, Patrick Williams III <address@hidden> wrote:
> Consider two virtual addresses that point to the same physical address.  One
> thread uses the first virtual address in a transaction; another thread
> writes to the second virtual address while the transaction is going on.
> This should cause the transaction to fail because the same physical address
> was involved.

Incidentally comparison against physical addresses, not virtual
addresses, is also the correct semantics for ARM load/store
exclusive instructions. At the moment we implement those with
a mechanism that is completely architecturally wrong but happens
to work for the stereotypical uses of those insns. If we ever
wanted to do it right then we'd need some way of catching
"some other CPU did a write to the physaddr we have an exclusive
lock for".

[Somebody pointed this out to me on IRC last night.]

-- PMM



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