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Re: [Qemu-devel] Help on TLB Flush

From: Peter Maydell
Subject: Re: [Qemu-devel] Help on TLB Flush
Date: Thu, 12 Feb 2015 21:57:21 +0000

On 12 February 2015 at 15:19, Alexander Graf <address@hidden> wrote:
> On 12.02.15 16:08, Mark Burton wrote:
>> Our question is - do we need this ‘sync’ (before the flush),
>> or can we actually allow CPU’s to flush themselves asynchronously….
> The respective target architecture specs will tell you. And I very much
> doubt that it is ok in most cases.

For ARM note that TLB maintenance operations do not have to
complete synchronously. They can be reordered relative to other
TLB maintenance ops or to loads or stores (by this CPU or
by other CPUs if this is a global invalidate). The only
requirement is that if the CPU that did the TLB maintenance
op executes a DMB (barrier) then the TLB op must finish
before the barrier completes execution. So you could split
the "kick off TLB invalidate" and "make sure all CPUs
are done" phases if you wanted. [cf v8 ARM ARM rev A.e
section D4.7.2 and in particular the subsection on
"ordering and completion".]

This only applies to ARM guests, of course. ("Other CPU
architectures are available." :-))

-- PMM

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