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[Qemu-devel] [PULL 08/12] target-arm: Add AArch32 guest support to KVM64
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/12] target-arm: Add AArch32 guest support to KVM64 |
Date: |
Fri, 13 Feb 2015 05:54:41 +0000 |
From: Greg Bellows <address@hidden>
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/kvm64.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 033babf..8cf3a62 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
ARMCPU *cpu = ARM_CPU(cs);
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
- !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
fprintf(stderr, "KVM is not supported for this guest CPU type\n");
return -EINVAL;
}
@@ -96,6 +96,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
cpu->psci_version = 2;
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
}
+ if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
+ }
/* Do KVM_ARM_VCPU_INIT ioctl */
ret = kvm_arm_vcpu_init(cs);
@@ -133,6 +136,13 @@ int kvm_arch_put_registers(CPUState *cs, int level)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
+ * AArch64 registers before pushing them out to 64-bit KVM.
+ */
+ if (!is_a64(env)) {
+ aarch64_sync_32_to_64(env);
+ }
+
for (i = 0; i < 31; i++) {
reg.id = AARCH64_CORE_REG(regs.regs[i]);
reg.addr = (uintptr_t) &env->xregs[i];
@@ -162,7 +172,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
/* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
- val = pstate_read(env);
+ if (is_a64(env)) {
+ val = pstate_read(env);
+ } else {
+ val = cpsr_read(env);
+ }
reg.id = AARCH64_CORE_REG(regs.pstate);
reg.addr = (uintptr_t) &val;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
@@ -242,7 +256,14 @@ int kvm_arch_get_registers(CPUState *cs)
if (ret) {
return ret;
}
- pstate_write(env, val);
+
+ env->aarch64 = ((val & PSTATE_nRW) == 0);
+ if (is_a64(env)) {
+ pstate_write(env, val);
+ } else {
+ env->uncached_cpsr = val & CPSR_M;
+ cpsr_write(env, val, 0xffffffff);
+ }
/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
* QEMU side we keep the current SP in xregs[31] as well.
@@ -256,6 +277,15 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
+ /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
+ * incoming AArch64 regs received from 64-bit KVM.
+ * We must perform this after all of the registers have been acquired from
+ * the kernel.
+ */
+ if (!is_a64(env)) {
+ aarch64_sync_64_to_32(env);
+ }
+
reg.id = AARCH64_CORE_REG(elr_el1);
reg.addr = (uintptr_t) &env->elr_el[1];
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
--
1.9.1
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 09/12] target-arm: A64: Fix shifts into sign bit, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 11/12] target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 10/12] target-arm: A64: Fix handling of rotate in logic_imm_decode_wmask, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 08/12] target-arm: Add AArch32 guest support to KVM64,
Peter Maydell <=
- [Qemu-devel] [PULL 05/12] target-arm: Add CPU property to disable AArch64, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 04/12] pci: Move PCI VGA to pci.mak, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 01/12] pci: Allocate PCIe host bridge PCI ID, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 03/12] arm: Add PCIe host bridge in virt machine, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 02/12] pci: Add generic PCIe host bridge, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 12/12] target-arm: A64: Avoid signed shifts in disas_ldst_pair(), Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 06/12] target-arm: Add feature parsing to virt, Peter Maydell, 2015/02/13
- [Qemu-devel] [PULL 07/12] target-arm: Add 32/64-bit register sync, Peter Maydell, 2015/02/13
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2015/02/13
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2015/02/13