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Re: [Qemu-devel] Help on TLB Flush

From: Mark Burton
Subject: Re: [Qemu-devel] Help on TLB Flush
Date: Fri, 13 Feb 2015 10:37:43 +0100

the memory barrier is on the cpu requesting the flush isn’t it (not on the CPU 
that is being flushed)?

> On 13 Feb 2015, at 10:34, Paolo Bonzini <address@hidden> wrote:
> On 12/02/2015 22:57, Peter Maydell wrote:
>> The only
>> requirement is that if the CPU that did the TLB maintenance
>> op executes a DMB (barrier) then the TLB op must finish
>> before the barrier completes execution. So you could split
>> the "kick off TLB invalidate" and "make sure all CPUs
>> are done" phases if you wanted. [cf v8 ARM ARM rev A.e
>> section D4.7.2 and in particular the subsection on
>> "ordering and completion".]
> You can just make DMB start a new translation block.  Then when the TLB
> flush helpers call cpu_exit() or cpu_interrupt() the flush request is
> serviced.
> Paolo

         +44 (0)20 7100 3485 x 210
 +33 (0)5 33 52 01 77x 210

        +33 (0)603762104

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