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Re: [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple hos

From: Marcel Apfelbaum
Subject: Re: [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple host bridges
Date: Mon, 16 Feb 2015 15:29:42 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0

On 02/16/2015 03:00 PM, Alexander Graf wrote:

On 16.02.15 10:54, Marcel Apfelbaum wrote:
From: Marcel Apfelbaum <address@hidden>

Instead of assuming it has only one bus, it
enumerates all the host bridges until it finds
the one with bus number corresponding with the
config register.

Signed-off-by: Marcel Apfelbaum <address@hidden>

Hi Alexander,
Thank you for the review.

How 440 specific is this? Wouldn't we need similar code for q35 and gpxe?
For gpxe: I have no idea.
For Q35: PCI Express have native support for extra root bridges by
having multiple Root Complexes(RC), but in this case each RC
handles its separate configuration space.

It may be possible to use the same hack as in PC to expose a
PCIe Root Port as a different host bridge and a primary bus behind
it, but it is out of this series scope.

The series aims to address the limitation that PC machines support
NUMA nodes for CPU/memory but not PCI.

Anyway, we can move the code when neeeded, but since it will
take some and the implementation is not certain, for the moment
is 440 specific.



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