[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 6/7] target-arm: Ignore low bit of PC in M-profile ex
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 6/7] target-arm: Ignore low bit of PC in M-profile exception return |
Date: |
Mon, 16 Mar 2015 12:40:17 +0000 |
For the ARM M-profile cores, exception return pops various registers
including the PC from the stack. The architecture defines that if the
lowest bit in the new PC value is set (ie the PC is not halfword
aligned) then behaviour is UNPREDICTABLE. In practice hardware
implementations seem to simply ignore the low bit, and some buggy
RTOSes incorrectly rely on this. QEMU's behaviour was architecturally
permitted, but bringing QEMU into line with the hardware behaviour
allows more guest code to run. We log the situation as a guest error.
This was reported as LP:1428657.
Reported-by: Anders Esbensen <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7fe3d14..10886c5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4334,6 +4334,16 @@ static void do_v7m_exception_exit(CPUARMState *env)
env->regs[12] = v7m_pop(env);
env->regs[14] = v7m_pop(env);
env->regs[15] = v7m_pop(env);
+ if (env->regs[15] & 1) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "M profile return from interrupt with misaligned "
+ "PC is UNPREDICTABLE\n");
+ /* Actual hardware seems to ignore the lsbit, and there are several
+ * RTOSes out there which incorrectly assume the r15 in the stack
+ * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
+ */
+ env->regs[15] &= ~1U;
+ }
xpsr = v7m_pop(env);
xpsr_write(env, xpsr, 0xfffffdff);
/* Undo stack alignment. */
--
1.9.1
- [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 5/7] target-arm: Fix handling of STM (user) with r15 in register list, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 4/7] hw/intc/arm_gic: Initialize the vgic in the realize function, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 6/7] target-arm: Ignore low bit of PC in M-profile exception return,
Peter Maydell <=
- [Qemu-devel] [PULL 7/7] linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 2/7] target-arm: fix get_phys_addr_v6/SCTLR_AFE access check, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 1/7] target-arm: convert check_ap to ap_to_rw_prot, Peter Maydell, 2015/03/16
- [Qemu-devel] [PULL 3/7] target-arm: get_phys_addr_lpae: more xn control, Peter Maydell, 2015/03/16
- Re: [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/03/16