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[Qemu-devel] [PATCH V6 for-2.3 17/26] hw/acpi: add _CRS method for extra
From: |
Marcel Apfelbaum |
Subject: |
[Qemu-devel] [PATCH V6 for-2.3 17/26] hw/acpi: add _CRS method for extra root busses |
Date: |
Thu, 19 Mar 2015 20:52:52 +0200 |
Save the IO/mem/bus numbers ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Signed-off-by: Marcel Apfelbaum <address@hidden>
---
hw/i386/acpi-build.c | 138 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4964d6b..fe9bb5c 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -734,6 +734,137 @@ static Aml *build_prt(void)
return method;
}
+typedef struct CrsRangeEntry {
+ uint64_t base;
+ uint64_t limit;
+} CrsRangeEntry;
+
+static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
+{
+ CrsRangeEntry *entry;
+
+ entry = g_malloc(sizeof(*entry));
+ entry->base = base;
+ entry->limit = limit;
+
+ g_ptr_array_add(ranges, entry);
+}
+
+static void crs_range_free(gpointer data)
+{
+ CrsRangeEntry *entry = (CrsRangeEntry *)data;
+ g_free(entry);
+}
+
+static Aml *build_crs(PCIHostState *host,
+ GPtrArray *io_ranges, GPtrArray *mem_ranges)
+{
+ Aml *crs = aml_resource_template();
+ uint8_t max_bus = pci_bus_num(host->bus);
+ uint8_t type;
+ int devfn;
+
+ for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
+ int i;
+ uint64_t range_base, range_limit;
+ PCIDevice *dev = host->bus->devices[devfn];
+
+ if (!dev) {
+ continue;
+ }
+
+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
+ PCIIORegion *r = &dev->io_regions[i];
+
+ range_base = r->addr;
+ range_limit = r->addr + r->size - 1;
+
+ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+ aml_append(crs,
+ aml_word_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0,
+ range_base,
+ range_limit,
+ 0,
+ range_limit - range_base + 1));
+ crs_range_insert(io_ranges, range_base, range_limit);
+ } else { /* "memory" */
+ aml_append(crs,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed,
+ aml_max_fixed, aml_non_cacheable,
+ aml_ReadWrite,
+ 0,
+ range_base,
+ range_limit,
+ 0,
+ range_limit - range_base + 1));
+ crs_range_insert(mem_ranges, range_base, range_limit);
+ }
+ }
+
+ type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
+ if (type == PCI_HEADER_TYPE_BRIDGE) {
+ uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
+ if (subordinate > max_bus) {
+ max_bus = subordinate;
+ }
+
+ range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
+ range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
+ aml_append(crs,
+ aml_word_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0,
+ range_base,
+ range_limit,
+ 0,
+ range_limit - range_base + 1));
+ crs_range_insert(io_ranges, range_base, range_limit);
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+ aml_append(crs,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed,
+ aml_max_fixed, aml_non_cacheable,
+ aml_ReadWrite,
+ 0,
+ range_base,
+ range_limit,
+ 0,
+ range_limit - range_base + 1));
+ crs_range_insert(mem_ranges, range_base, range_limit);
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+ aml_append(crs,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed,
+ aml_max_fixed, aml_non_cacheable,
+ aml_ReadWrite,
+ 0,
+ range_base,
+ range_limit,
+ 0,
+ range_limit - range_base + 1));
+ crs_range_insert(mem_ranges, range_base, range_limit);
+ }
+ }
+
+ aml_append(crs,
+ aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
+ 0,
+ pci_bus_num(host->bus),
+ max_bus,
+ 0,
+ max_bus - pci_bus_num(host->bus) + 1));
+
+ return crs;
+}
+
static void
build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -744,6 +875,8 @@ build_ssdt(GArray *table_data, GArray *linker,
unsigned acpi_cpus = guest_info->apic_id_limit;
Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
PCIHostState *snooped_host;
+ GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
int i;
ssdt = init_aml_allocator();
@@ -773,9 +906,14 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A03")));
aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
aml_append(dev, build_prt());
+ crs = build_crs(host, io_ranges, mem_ranges);
+ aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(ssdt, scope);
}
+
+ g_ptr_array_free(io_ranges, true);
+ g_ptr_array_free(mem_ranges, true);
}
scope = aml_scope("\\_SB.PCI0");
--
2.1.0
- [Qemu-devel] [PATCH V6 for-2.3 07/26] acpi: add aml_increment() term, (continued)
- [Qemu-devel] [PATCH V6 for-2.3 07/26] acpi: add aml_increment() term, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 09/26] hw/pci: move pci bus related code to separate files, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 08/26] acpi: add aml_while() term, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 13/26] hw/pci-host: introduce TYPE_PCI_HOST_BRIDGE_SNOOPED interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 14/26] hw/pci-host/piix: implement TYPE_PCI_HOST_BRIDGE_SNOOPED interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 10/26] hw/pci: made pci_bus_is_root a PCIBusClass method, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 11/26] hw/pci: made pci_bus_num a PCIBusClass method, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 16/26] hw/apci: add _PRT method for extra PCI root busses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 15/26] hw/acpi: add support for i440fx 'snooping' root busses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 12/26] hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 17/26] hw/acpi: add _CRS method for extra root busses,
Marcel Apfelbaum <=
- [Qemu-devel] [PATCH V6 for-2.3 19/26] hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 21/26] hw/pci: inform bios if the system has extra pci root buses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 18/26] hw/acpi: remove from root bus 0 the crs resources used by other busses., Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 25/26] apci: fix PXB behaviour if used with unsupported BIOS, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 22/26] hw/pxb: add map_irq func, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 20/26] hw/pci: introduce PCI Expander Bridge (PXB), Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 24/26] hw/pxb: add numa_node parameter, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 26/26] docs: Add PXB documentation, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 23/26] hw/pci_bus: add support for NUMA nodes, Marcel Apfelbaum, 2015/03/19
- Re: [Qemu-devel] [PATCH V6 for-2.3 00/26] hw/pc: implement multiple primary busses for pc machines, Paolo Bonzini, 2015/03/19