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[Qemu-devel] [PATCH V6 for-2.3 18/26] hw/acpi: remove from root bus 0 th
From: |
Marcel Apfelbaum |
Subject: |
[Qemu-devel] [PATCH V6 for-2.3 18/26] hw/acpi: remove from root bus 0 the crs resources used by other busses. |
Date: |
Thu, 19 Mar 2015 20:52:53 +0200 |
If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.
Signed-off-by: Marcel Apfelbaum <address@hidden>
---
hw/i386/acpi-build.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 77 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fe9bb5c..ab7ebeb 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -756,6 +756,50 @@ static void crs_range_free(gpointer data)
g_free(entry);
}
+static gint crs_range_compare(gconstpointer a, gconstpointer b)
+{
+ CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
+ CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
+
+ return (int64_t)entry_a->base - (int64_t)entry_b->base;
+}
+
+/*
+ * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
+ * interval, computes the 'free' ranges from the same interval.
+ * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
+ * will return { [base - a1], [a2 - b1], [b2 - limit] }.
+ */
+static void crs_replace_with_free_ranges(GPtrArray *ranges,
+ uint64_t start, uint64_t end)
+{
+ GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ uint64_t free_base = start;
+ int i;
+
+ g_ptr_array_sort(ranges, crs_range_compare);
+ for (i = 0; i < ranges->len; i++) {
+ CrsRangeEntry *used = g_ptr_array_index(ranges, i);
+
+ if (free_base < used->base) {
+ crs_range_insert(free_ranges, free_base, used->base - 1);
+ }
+
+ free_base = used->limit + 1;
+ }
+
+ if (free_base < end) {
+ crs_range_insert(free_ranges, free_base, end);
+ }
+
+ g_ptr_array_set_size(ranges, 0);
+ for (i = 0; i < free_ranges->len; i++) {
+ g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
+ }
+
+ g_ptr_array_free(free_ranges, false);
+}
+
static Aml *build_crs(PCIHostState *host,
GPtrArray *io_ranges, GPtrArray *mem_ranges)
{
@@ -877,6 +921,8 @@ build_ssdt(GArray *table_data, GArray *linker,
PCIHostState *snooped_host;
GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ CrsRangeEntry *entry;
+ int root_bus_limit = 0xFF;
int i;
ssdt = init_aml_allocator();
@@ -899,6 +945,10 @@ build_ssdt(GArray *table_data, GArray *linker,
PCIHostState *host = g_ptr_array_index(snooping_hosts, i);
uint8_t bus_num = pci_bus_num(host->bus);
+ if (bus_num < root_bus_limit) {
+ root_bus_limit = bus_num - 1;
+ }
+
scope = aml_scope("\\_SB");
dev = aml_device("PC%.02X", bus_num);
aml_append(dev,
@@ -911,9 +961,6 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(scope, dev);
aml_append(ssdt, scope);
}
-
- g_ptr_array_free(io_ranges, true);
- g_ptr_array_free(mem_ranges, true);
}
scope = aml_scope("\\_SB.PCI0");
@@ -921,26 +968,40 @@ build_ssdt(GArray *table_data, GArray *linker,
crs = aml_resource_template();
aml_append(crs,
aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
- 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
+ 0x0000, 0x0, root_bus_limit,
+ 0x0000, root_bus_limit + 1));
aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
aml_append(crs,
aml_word_io(aml_min_fixed, aml_max_fixed,
aml_pos_decode, aml_entire_range,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
+
+ crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
+ for (i = 0; i < io_ranges->len; i++) {
+ entry = g_ptr_array_index(io_ranges, i);
+ aml_append(crs,
+ aml_word_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0x0000, entry->base, entry->limit,
+ 0x0000, entry->limit - entry->base + 1));
+ }
+
aml_append(crs,
aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
aml_cacheable, aml_ReadWrite,
0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
- aml_append(crs,
- aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
- aml_non_cacheable, aml_ReadWrite,
- 0, pci->w32.begin, pci->w32.end - 1, 0,
- pci->w32.end - pci->w32.begin));
+
+ crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
+ for (i = 0; i < mem_ranges->len; i++) {
+ entry = g_ptr_array_index(mem_ranges, i);
+ aml_append(crs,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
+ aml_non_cacheable, aml_ReadWrite,
+ 0, entry->base, entry->limit,
+ 0, entry->limit - entry->base + 1));
+ }
+
if (pci->w64.begin) {
aml_append(crs,
aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
@@ -963,6 +1024,9 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
+ g_ptr_array_free(io_ranges, true);
+ g_ptr_array_free(mem_ranges, true);
+
/* reserve PCIHP resources */
if (pm->pcihp_io_len) {
dev = aml_device("PHPR");
--
2.1.0
- [Qemu-devel] [PATCH V6 for-2.3 13/26] hw/pci-host: introduce TYPE_PCI_HOST_BRIDGE_SNOOPED interface, (continued)
- [Qemu-devel] [PATCH V6 for-2.3 13/26] hw/pci-host: introduce TYPE_PCI_HOST_BRIDGE_SNOOPED interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 14/26] hw/pci-host/piix: implement TYPE_PCI_HOST_BRIDGE_SNOOPED interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 10/26] hw/pci: made pci_bus_is_root a PCIBusClass method, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 11/26] hw/pci: made pci_bus_num a PCIBusClass method, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 16/26] hw/apci: add _PRT method for extra PCI root busses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 15/26] hw/acpi: add support for i440fx 'snooping' root busses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 12/26] hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 17/26] hw/acpi: add _CRS method for extra root busses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 19/26] hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 21/26] hw/pci: inform bios if the system has extra pci root buses, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 18/26] hw/acpi: remove from root bus 0 the crs resources used by other busses.,
Marcel Apfelbaum <=
- [Qemu-devel] [PATCH V6 for-2.3 25/26] apci: fix PXB behaviour if used with unsupported BIOS, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 22/26] hw/pxb: add map_irq func, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 20/26] hw/pci: introduce PCI Expander Bridge (PXB), Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 24/26] hw/pxb: add numa_node parameter, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 26/26] docs: Add PXB documentation, Marcel Apfelbaum, 2015/03/19
- [Qemu-devel] [PATCH V6 for-2.3 23/26] hw/pci_bus: add support for NUMA nodes, Marcel Apfelbaum, 2015/03/19
- Re: [Qemu-devel] [PATCH V6 for-2.3 00/26] hw/pc: implement multiple primary busses for pc machines, Paolo Bonzini, 2015/03/19