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Re: [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for G
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR |
Date: |
Tue, 14 Apr 2015 20:25:31 +0100 |
On 30 October 2014 at 22:12, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> Grouping (GICv2) and Security Extensions change the behaviour of reads
> of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> ---
> hw/intc/arm_gic.c | 29 ++++++++++++++++++++++++++++-
> hw/intc/gic_internal.h | 1 +
> 2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 9b021d7..15fd660 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -329,6 +329,33 @@ uint8_t gic_get_running_priority(GICState *s, int cpu)
> }
> }
>
> +uint16_t gic_get_current_pending_irq(GICState *s, int cpu)
> +{
> + bool isGrp0;
> + uint16_t pendingId = s->current_pending[cpu];
> +
> + if (pendingId < GIC_MAXIRQ && (s->revision >= 2 || s->security_extn)) {
> + isGrp0 = GIC_TEST_GROUP0(pendingId, (1 << cpu));
> + if ((isGrp0 && !s->enabled_grp[0])
> + || (!isGrp0 && !s->enabled_grp[1])) {
> + return 1023;
> + }
> + if (s->security_extn) {
> + if (isGrp0 && ns_access()) {
> + /* Group0 interrupts hidden from Non-secure access */
> + return 1023;
> + }
> + if (!isGrp0 && !ns_access()
> + && !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) {
> + /* Group1 interrupts only seen by Secure access if
> + * AckCtl bit set. */
> + return 1022;
> + }
> + }
> + }
> + return pendingId;
> +}
Some coding style nits about var name capitalisation and
multiline comment style, but otherwise OK.
-- PMM
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