|
From: | Greg Bellows |
Subject: | Re: [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled |
Date: | Wed, 22 Apr 2015 09:04:25 -0500 |
Signed-off-by: Sergey Fedorov <address@hidden>
---
target-arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 986f04c..327b1e5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_EL3);
/* Disable the security extension feature bits in the processor feature
- * register as well. This is id_pfr1[7:4].
+ * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
*/
cpu->id_pfr1 &= ~0xf0;
+ cpu->id_aa64pfr0 &= ~0xf000;
}
register_cp_regs_for_features(cpu);
--
2.3.4
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