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Re: [Qemu-devel] [PATCH target-arm v5 00/14] Next Generation Xilinx Zynq
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v5 00/14] Next Generation Xilinx Zynq SoC |
Date: |
Fri, 24 Apr 2015 13:18:54 -0700 |
On Fri, Apr 24, 2015 at 12:31 PM, Peter Crosthwaite
<address@hidden> wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs are added. The
> pre-existing models for GEM and UART are not SoC friendly (no visible
> state struct), so those are refactored for SoC.
>
> Create a model of the EP108 board. Currently this doesn't have any
> EP108 specific features but is a usable board exposing the user visible
> features of the raw SoC.
>
> See individual patches for detailed change logs.
>
> changed since v4:
> Addressed PMM and Alistair Reviews
>
> changed since v3:
> Included CPU thread kick fix
> Addressed Alistair review
>
> changed since v2:
> Fix CPU child prop adder
> Add DTS compat string
>
> changed since v1:
> Addressed Alistair review (individual changes on resp. patches)
> Changed board name to EP108
> Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review)
>
> Regards,
> Peter
>
>
> Peter Crosthwaite (14):
> target-arm: cpu64: generalise name of A57 regs
> target-arm: cpu64: Add support for cortex-a53
> arm: Introduce Xilinx ZynqMP SoC
> arm: xlnx-zynqmp: Add GIC
> arm: xlnx-zynqmp: Connect CPU Timers to GIC
> net: cadence_gem: Clean up variable names
> net: cadence_gem: Split state struct and type into header
> arm: xilinx-zynqmp: Add GEM support
> char: cadence_uart: Clean up variable names
> char: cadence_uart: Split state struct and type into header
> arm: xilinx-zynqmp: Add UART support
> arm: Add xlnx-ep108 machine
> arm: xilinx-ep108: Add external RAM
> arm: xilinx-ep108: Add bootloading
>
> default-configs/aarch64-softmmu.mak | 2 +-
> hw/arm/Makefile.objs | 1 +
> hw/arm/xlnx-ep108.c | 82 ++++++++++++++++
> hw/arm/xlnx-zynqmp.c | 188
> ++++++++++++++++++++++++++++++++++++
> hw/char/cadence_uart.c | 115 +++++++++-------------
> hw/net/cadence_gem.c | 95 ++++++------------
> include/hw/arm/xlnx-zynqmp.h | 46 +++++++++
> include/hw/char/cadence_uart.h | 53 ++++++++++
> include/hw/net/cadence_gem.h | 73 ++++++++++++++
> target-arm/cpu64.c | 61 +++++++++++-
> 10 files changed, 574 insertions(+), 142 deletions(-)
> create mode 100644 hw/arm/xlnx-ep108.c
> create mode 100644 hw/arm/xlnx-zynqmp.c
> create mode 100644 include/hw/arm/xlnx-zynqmp.h
> create mode 100644 include/hw/char/cadence_uart.h
> create mode 100644 include/hw/net/cadence_gem.h
>
> --
> 2.3.6.3.g2cc70ee
>
>
Sorry this has a bug in it. Please ignore. V6 on way. The has_el3
change shouldn't be in.
Regards,
Peter
- [Qemu-devel] [PATCH target-arm v5 05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC, (continued)
- [Qemu-devel] [PATCH target-arm v5 05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 03/14] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 04/14] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 07/14] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 06/14] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 10/14] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 09/14] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 14/14] arm: xilinx-ep108: Add bootloading, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 12/14] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/04/24
- [Qemu-devel] [PATCH target-arm v5 13/14] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/04/24
- Re: [Qemu-devel] [PATCH target-arm v5 00/14] Next Generation Xilinx Zynq SoC,
Peter Crosthwaite <=