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[Qemu-devel] [PULL 13/17] target-arm: Use attribute info to handle user-
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/17] target-arm: Use attribute info to handle user-only watchpoints |
Date: |
Mon, 27 Apr 2015 16:20:41 +0100 |
Now that we have memory access attribute information in the watchpoint
checking code, we can correctly implement handling of watchpoints
which should match only on userspace accesses, where LDRT/STRT/LDT/STT
from EL1 are treated as userspace accesses.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
target-arm/op_helper.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 7713022..4a8c4e0 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -602,13 +602,22 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
int pac, hmc, ssc, wt, lbn;
/* TODO: check against CPU security state when we implement TrustZone */
bool is_secure = false;
+ int access_el = arm_current_el(env);
if (is_wp) {
- if (!env->cpu_watchpoint[n]
- || !(env->cpu_watchpoint[n]->flags & BP_WATCHPOINT_HIT)) {
+ CPUWatchpoint *wp = env->cpu_watchpoint[n];
+
+ if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
return false;
}
cr = env->cp15.dbgwcr[n];
+ if (wp->hitattrs.user) {
+ /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
+ * match watchpoints as if they were accesses done at EL0, even if
+ * the CPU is at EL1 or higher.
+ */
+ access_el = 0;
+ }
} else {
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
@@ -649,15 +658,7 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
break;
}
- /* TODO: this is not strictly correct because the LDRT/STRT/LDT/STT
- * "unprivileged access" instructions should match watchpoints as if
- * they were accesses done at EL0, even if the CPU is at EL1 or higher.
- * Implementing this would require reworking the core watchpoint code
- * to plumb the mmu_idx through to this point. Luckily Linux does not
- * rely on this behaviour currently.
- * For breakpoints we do want to use the current CPU state.
- */
- switch (arm_current_el(env)) {
+ switch (access_el) {
case 3:
case 2:
if (!hmc) {
--
1.9.1
- [Qemu-devel] [PULL 00/17] target-arm queue, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 17/17] Allow ARMv8 SCR.SMD updates, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 14/17] target-arm: Check watchpoints against CPU security state, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 16/17] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 01/17] memory: Define API for MemoryRegionOps to take attrs and return status, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 15/17] target-arm: rename c1_coproc to cpacr_el1, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 12/17] target-arm: Add user-mode transaction attribute, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 13/17] target-arm: Use attribute info to handle user-only watchpoints,
Peter Maydell <=
- [Qemu-devel] [PULL 11/17] target-arm: Use correct memory attributes for page table walks, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 10/17] target-arm: Honour NS bits in page tables, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 05/17] exec.c: Convert subpage memory ops to _with_attrs, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 03/17] Make CPU iotlb a structure rather than a plain hwaddr, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 06/17] exec.c: Make address_space_rw take transaction attributes, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 07/17] exec.c: Add new address_space_ld*/st* functions, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 09/17] Switch non-CPU callers from ld/st*_phys to address_space_ld/st*, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 02/17] memory: Replace io_mem_read/write with memory_region_dispatch_read/write, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 08/17] exec.c: Capture the memory attributes for a watchpoint hit, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 04/17] Add MemTxAttrs to the IOTLB, Peter Maydell, 2015/04/27