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[Qemu-devel] [RFC 2/5] arm64: Add PMOVSCLR_EL0 register
From: |
Christopher Covington |
Subject: |
[Qemu-devel] [RFC 2/5] arm64: Add PMOVSCLR_EL0 register |
Date: |
Thu, 30 Apr 2015 14:14:24 -0400 |
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington <address@hidden>
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6aeb77c..c9463cb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -904,6 +904,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.accessfn = pmreg_access,
.writefn = pmovsr_write,
.raw_writefn = raw_write },
+ { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
+ .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .accessfn = pmreg_access,
+ .writefn = pmovsr_write,
+ .raw_writefn = raw_write },
/* Unimplemented so WI. */
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
--
1.9.1