[Qemu-devel] [PATCH v3 0/4] apic: Implement MSI RH bit handling, lowpri IRQ delivery

[James Sullivan]

Changes in v2:
    * Merged in low priority IRQ delivery implementation to RH bit
    handling implementation, since both rely on the same helper
    functions for priority arbitration.
    * Corrected use of MSI data register => addr register when setting
    msi_redir_hint in apic_send_msi().
Changes in v3:
    * Fixed apic_get_arb_pri() to match the algorithm outlined in the
    AMD manual vs. the (incorrect?) Intel manual.
    * Removed apic_lowest_prio() in favour of performing the arbitration
    within apic_get_delivery_bitmask() while we iterate through the
    LAPICs (saves a few calls to an iteration over all LAPICs).
    * Modified delivery of APIC_DM_LOWPRI to be identical to
    APIC_DM_FIXED (since we account for arbitration when setting the
    delivery bitmask)

This set of patches adds the following features to QEMU:
    * Low priority delivery arbitration. Currently the first present CPU
    is always selected when lowpri delivery mode is used, and no
    arbitration is performed. Implemented arbitration in
    apic_bus_deliver() by adding the following functions:
        1) apic_get_arb_pri(APICCommonState *s)
        2) apic_compare_prio(APICCommonState *s1, APICCommonState *s2);
        3) apic_lowest_prio(const uint32_t *deliver_bitmask)
    * RH Bit handling for MSI messages. See below.

Currently, there is no handling of the MSI RH bit. This patch implements 
the following logic:

* DM=0, RH=*  : Physical destination mode. Interrupt is delivered to
                    the LAPIC with the matching APIC ID. (Subject to
                    the usual restrictions, i.e. no broadcast dest)
* DM=1, RH=0  : Logical destination mode without redirection. Interrupt
                    is delivered to all LAPICs in the logical group 
                    specified by the IRQ's destination map and delivery
                    mode.
* DM=1, RH=1  : Logical destination mode with redirection. Interrupt
                    is delivered only to the lowest priority LAPIC in the 
                    logical group specified by the dest map and the
                    delivery mode. Delivery semantics are otherwise
                    specified by the delivery_mode of the IRQ, which
                    is unchanged.

These changes reflect those made in the KVM in
http://www.spinics.net/lists/kvm/msg114915.html ("kvm: x86: Implement
handling of RH=1 for MSI delivery in KVM"), which is queued for 4.2.

James Sullivan (4):
  apic: Implement LAPIC low priority arbitration functions
  apic: Set and pass in RH bit for MSI interrupts
  apic: Add helper functions apic_match_dest,
    apic_match_[physical,logical]_dest
  apic: Handle RH=1 and lowpri delivery mode in
    apic_get_delivery_bitmask()

 hw/intc/apic.c         | 130 ++++++++++++++++++++++++++++++++-----------------
 hw/intc/ioapic.c       |   2 +-
 include/hw/i386/apic.h |   3 +-
 trace-events           |   2 +-
 4 files changed, 90 insertions(+), 47 deletions(-)

-- 
2.3.5